MPCBL0010
Table 83. | IPMC Register Legend (Continued) | |
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| Address | Function |
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| 03h | PostCodeHigh (I/O 81) |
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| Reserved | |
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| 06h | LED Color Control |
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| 07h | LED Control |
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| Reserved | |
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| AMC B1 | |
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| AMC B2 | |
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| Reserved | |
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| 18h | CPU 0 VIDs |
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| 19h | CPU 0 Status |
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| Reserved | |
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| 20h | ADCs Grab Control |
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| 21h | ADC1 Reading |
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| 22h | ADC2 Reading |
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| 23h | Reserved |
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| 24h | Fabric Control 1 |
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| 25h | Fabric Control 2 |
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| 26h | Reserved |
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| 27h | Reset Source |
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| 28h | Frimware Hub Control |
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| 29h | Reset Events |
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| 2Ah | Crosspoint Switch Control |
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| 2Bh | Crosspoint Switch Data |
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| 2Ch | Reserved |
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| 2Dh | Miscellaneous Control and Status |
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| Reserved | |
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| FEh | POST Code Register (if enabled) |
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| 1FFh | Version |
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Table 84. | SBC Control 00h |
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| Address | Action | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
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| Read | 0 | BoardON | TurnX | PwrBtn | LTYPE | LTEST | UART | BRST |
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| 00h | Write | HT0 | NU | NU | PwrBtn(1) | LTYPE | LTEST | UART | BRST |
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| PowerUp | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
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BRST: Board Reset; set this bit for a minimum of 16ms to reset the SBC.
LTEST: Lamp test; set this bit to perform a global lamp test on all the front panel LEDs.
Intel NetStructure® MPCBL0010 Single Board Computer |
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Technical Product Specification | October 2006 |
104 | Order Number: 304120 |
