Intel NetStructure® MPCBL0010 Single Board Computer
October 2006 Technical Product Specification
Order Number: 304120 101
Addressing—MPCBL0010 SBC
DRVCLKA1: Drives transmission clock CLKA for Adva ncedMC B2. Thi s bit is forced to 0
when AdvancedMC B2 is absent or unpowered.
DRVCLKA0: Drives transmission clock CLKA for Adva ncedMC B1. Thi s bit is forced to 0
when AdvancedMC B1 is absent or unpowered.
DRVCLK3B: Enables MLVDS buffer to drive CLK3B to the backplane. This bit is forced
to 0 until the IPMC authorizes it.
DRVCLK3A: Enables MLVDS buffer to drive CLK3A to the backplane. This bit is forced
to 0 until the IPMC authorizes it.
TXREF1_SEL[2..0]: Transmission reference clock for AdvancedMC B2 selection (See
Tabl e 78 )
TXREF0_SEL[2..0]: Transmission reference clock for AdvancedMC B1 selection (See
Tabl e 78) The transmission frequency is selected according to Tab le 78:
Notes:
† 8 kHz or 16 MHz can be selected by bit 8K_16M in telecom clock register 1.
‡ One frequency can be selected by bits E3DS3 and E3DS3OC3 in telecom clock register 0.
IRQTST: Interrupt test -- the state of this bit is ORed with the real interrupt.
Note: This bit is for software testing. Ignore it in normal operation. A "1" asserts the interrupt
request.
TEST: Ignores IPMC and shelf manager authorization.
Table 77. Telecom Clock Register 3 0A0Bh
AddressAction D7 D6 D5D4D3D2D1D0
0xA0B
Read DRVCLK3B DRVCLK3A TXREF1_SEL[2..0] TXREF0_SEL[2..0]
Write DRVCLK3B DRVCLK3A TXREF1_SEL[2..0] TXREF0_SEL[2..0]
Reset 0 0 000 000
Table 78. Transmission Frequency Selection
TXREFx_SEL[2..0] Transmission Clock Frequency
000 1.544 MHz (T1, J1)
001 2.048 MHz (E1)
010 4.096 MHz (E1)
011 6.312 MHz (J2)
100 8.192 MHz (E1)
101 8 kHz / 16.384 MHz† (E1, T1, J1, J2)
110 19.44 MHz (OC3, 12/STM-1, 4)
111 34.368 / 44.736 MHz‡ (E3, T3) or 8.592 / 11.184 MHz
Table 79. Telecom Clock Register 4 0A0Ch
Address Action D7 D6 D5 D4 D3 D2 D1 D0
0xA0C
Read NU NU NU NU NU IRQTST RESET TEST
Write NU NU NU NU NU IRQTST RESET TEST
Reset X X X X X 0 1 0