DRVCLKA1: Drives transmission clock CLKA for AdvancedMC B2. This bit is forced to 0 when AdvancedMC B2 is absent or unpowered.
DRVCLKA0: Drives transmission clock CLKA for AdvancedMC B1. This bit is forced to 0 when AdvancedMC B1 is absent or unpowered.
Table 77. | Telecom Clock Register 3 0A0Bh |
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| Address | Action | D7 | D6 | D5 | D4 |
| D3 | D2 | D1 |
| D0 |
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| Read | DRVCLK3B | DRVCLK3A | TXREF1_SEL[2..0] |
| TXREF0_SEL[2..0] |
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| 0xA0B | Write | DRVCLK3B | DRVCLK3A | TXREF1_SEL[2..0] |
| TXREF0_SEL[2..0] |
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| Reset | 0 | 0 | 000 |
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| 000 |
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DRVCLK3B: Enables MLVDS buffer to drive CLK3B to the backplane. This bit is forced to 0 until the IPMC authorizes it.
DRVCLK3A: Enables MLVDS buffer to drive CLK3A to the backplane. This bit is forced to 0 until the IPMC authorizes it.
TXREF1_SEL[2..0]: Transmission reference clock for AdvancedMC B2 selection (See Table 78 )
TXREF0_SEL[2..0]: Transmission reference clock for AdvancedMC B1 selection (See Table 78) The transmission frequency is selected according to Table 78:
Table 78. | Transmission Frequency Selection |
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| TXREFx_SEL[2..0] |
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| Transmission Clock Frequency |
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| 000 |
| 1.544 | MHz (T1, J1) |
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| 001 |
| 2.048 | MHz (E1) |
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| 010 |
| 4.096 | MHz (E1) |
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| 011 |
| 6.312 | MHz (J2) |
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| 100 |
| 8.192 | MHz (E1) |
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| 8 kHz / 16.384 MHz† (E1, T1, J1, J2) |
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| 110 |
| 19.44 | MHz (OC3, |
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| 34.368 / 44.736 MHz‡ (E3, T3) or 8.592 / 11.184 MHz |
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| Notes: |
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| † 8 kHz or 16 MHz can be selected by bit 8K_16M in telecom clock register 1. |
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| ‡ One frequency can be selected by bits E3DS3 and E3DS3OC3 in telecom clock register 0. |
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Table 79. | Telecom Clock Register 4 0A0Ch |
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| Address | Action |
| D7 | D6 | D5 |
| D4 | D3 |
| D2 | D1 | D0 | ||
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| Read |
| NU |
| NU | NU |
| NU | NU |
| IRQTST | RESET | TEST | |
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| 0xA0C | Write |
| NU |
| NU | NU |
| NU | NU |
| IRQTST | RESET | TEST | |
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| Reset |
| X |
| X | X |
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| 0 |
| 1 | 0 |
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IRQTST: Interrupt test
Note: This bit is for software testing. Ignore it in normal operation. A "1" asserts the interrupt request.
TEST: Ignores IPMC and shelf manager authorization.
| Intel NetStructure® MPCBL0010 Single Board Computer |
October 2006 | Technical Product Specification |
Order Number: 304120 | 101 |
