Intel NetStructure® MPCBL0010 Single Board Computer
October 2006 Technical Product Specification
Order Number: 304120 125
Hardware Management Overview—MPCBL0010 SBC
Note: The event log reports both correctable memory errors (single-bit) and uncorrectable memory errors (double-bit or multi-bit). However, some double-bit errors are correctable and some are not. If a double-bit error occurs that is correctable, it will be logged as a correctable error (single-bit).Note: This IERR detection scheme differs in implementation on the MPCBL0010 SBC from “traditional” PC architecture. On the MPCBL0010 SBC, IERR is reported as part of SERR. When IERR occurs, the CPUis not automatically reset as on a traditional PC. You must use a BIOS or IPMC watchdog if your preference is to have the SBC reset itself automatically when this occurs.
Power Supply
OEM Power Good
reading type
08h
OEM
Event/
Reading
0x77
00h VCC Good 12V
When this bit is asserted, it means that
Power Good is normal.
01h VCC Todd 5V
02h VCC Good 3.3V
03h VCC Good 2.5V
04h VCC Good 1.8V
05h VCC Core 1.5V
06h VCC Good 1.2VV
07h VCC Good Core
AdvancedTCA FRU
Hot Swap F0h
07h M7
FRU Inactive
Refer to PICMG 3.0 Specification.
06h M6
FRU Activation Request
05h M5
FRU Activation In Progress
04h M4
FRU Active
03h M3
FRU Deactivation Request
02h M2
FRU Deactivation In Progress
01h M1
Communication Lost
00h M0
FRU Not Installed
IPMB Link Sensor F1h
00h IPMB A & B Disabled
Refer to PICMG 3.0 Specification.
01h IPMB A Enabled
IPMB B Disabled
02h IPMB A Disabled
IPMB B Enabled
03h IPMB A & B Enabled
Table 112. SEL Events Supported (Sheet 5 of 5)
Sensor Type Sensor
Type
Code
Sensor
Specific
Offset Event Description