MPCBL0010
Table 150. FPGA/PLD Serial Link Bit Definition
Bit | Write | Read |
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0 | 0 (to avoid spurious reset) | TelClock1: REFSEL |
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1 | 0 (to avoid spurious reset) | TelClock1: RSV0 |
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2 | 0 (to avoid spurious reset) | TelClock1: RSV1 |
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3 | TelClock4: Reset | TelClock2: UNLOCK |
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4 | TelClock0:E3DS30C3 | TelClock2: HOLDOVER |
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5 | TelClock0: E3DS3 | TelClock2: SEC_LOS |
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6 | TelClock0: FCS | TelClock2: PRI_LOS |
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7 | TelClock0: REFALIGN | TelClock5: Version(0) |
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8 | TelClock0: MS1 | TelClock5: Version(1) |
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9 | TelClock0: MS2 | TelClock5: Version(2) |
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10 | TelClock0: HO_LOS | TelClock5: Version(3) |
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11 | TelClock0: HWMODE | TelClock5: Version(4) |
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12 | TelClock1: SEL_RDNCLK | TelClock5: Version(5) |
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13 | TelClock1: SEL_REFFRQ | TelClock5: Version(6) |
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14 | TelClock1: 8K_16M | TelClock5: Version(7) |
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15 | TelClock1: SELCLK3A |
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16 | TelClock1: SELCLK3B |
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17 | TelClock2: DRVCLKA0 |
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18 | TelClock2: DRVCLKB0 |
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19 | TelClock2: DRVCLKA1 |
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20 | TelClock2: DRVCLKB1 |
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21 | TelClock3: TXREF0_SEL(0) |
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22 | TelClock3: TXREF0_SEL(1) |
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23 | TelClock3: TXREF0_SEL(2) |
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24 | TelClock3: TXREF1_SEL(0) |
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25 | TelClock3: TXREF1_SEL(1) |
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26 | TelClock3: TXREF1_SEL(2) |
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27 | TelClock3: DRVCLK3A |
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28 | TelClock3: DRVCLK3B |
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29 | TelClock4: TEST |
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30 | 0 (not used) |
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31 | 0 (not used) |
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Intel NetStructure® MPCBL0010 Single Board Computer |
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Technical Product Specification | October 2006 |
176 | Order Number: 304120 |
