Intel MPCBL0010 manual Bios Features, Introduction, Bios Flash Memory Organization

BIOS Features—MPCBL0010 SBC

6.0BIOS Features

6.1Introduction

The MPCBL0010 SBC uses an Intel/AMI* BIOS, which is stored in flash memory and updated using a disk-based program. In addition to the BIOS and BIOS setup program, the flash memory contains POST and Plug and Play support.

The BIOS displays a message during POST identifying the type of BIOS and a revision code. Refer to the Specification Update on the Documentation tab of the MPCBL0010 SBC web site at http://www.intel.com/design/telecom/products/cbp/atca/9445/ overview.htm for the latest default settings.

6.2BIOS Flash Memory Organization

The MPCBL0010 SBC contains two firmware hub (FWH) devices . (See Figure 1) The first is the Primary FWH, which holds the BIOS code that executes during POST. The second is the Backup FWH, which recovers the system when the Primary FWH is corrupted. The N82802AC FWH includes an 8 Mbit (1024 KByte) symmetrical flash memory device. Internally, the device is grouped into sixteen 64-KByte blocks that are individually erasable, lockable, and unlockable.

6.3Complementary Metal-Oxide Semiconductor (CMOS)

CMOS RAM is a nonvolatile storage that stores data needed by the BIOS. The data consists of certain onboard configurable settings, including time and date. CMOS resides in the 6300ESB ICH and is powered by the Supercap when the blade is power off. The settings in the BIOS setup menu are stored in the CMOS RAM and are often called CMOS settings.

6.4Redundant BIOS Functionality

MPCBL0010 SBC hardware has two flash banks for BIOS where redundant copies are stored. BIOS bank selection logic is connected to the IPMC, and the IPMC firmware allows selection of the BIOS bank.

By default, firmware selects BIOS bank 0. BIOS executes code off this flash and performs checksum validation of its operational code. This checksum occurs in the boot block of the BIOS. If the boot block detects a checksum failure in the remainder of the BIOS, it notifies the IPMC of the failure.

In case of failure, the IPMC firmware:

1.Asserts the RESET pin on the processor

2.Switches the flash bank

3.De-asserts the RESET pin on the processor, allowing BIOS to execute off the second flash bank

An application running on a non-Plug and Play operating system can obtain the SMBIOS information.

	Intel NetStructure® MPCBL0010 Single Board Computer
October 2006	Technical Product Specification
Order Number: 304120	57