Intel Intel NetStructure Single Board Computer, MPCBL0010 manual Ipmc, Telecom Clock

MPCBL0010 SBC—Feature Overview

Current values here indicate the maximum that can be delivered by design and do not reflect the current actually provided on the MPCBL0010 SBC. Additionally, each converter has design margin. The maximum current that can be drawn by the SBC in operation is 200 Watts, conforming with the AdvancedTCA 3.0 specification.

2.2.7.4Processor Voltage Regulator Module (VRM)

The Voltage Regulator Module (VRM) provides core power to the Low Voltage Xeon processor. The input to the VRM is connected to the +12 V power rail.

The VRM controller is designed to support the processor core voltages selected by the voltage identification (VID) pins on the processor. The VRM is disabled until all other voltage converters indicate “power good.” The voltage regulator module is designed to support one Low Voltage Xeon at up to 60 A of current.

2.2.7.5IPMC Subsystem Standby Power

The IPMC subsystem standby power is 3.3 V suspend, as described in Section 2.2.7.3.

2.2.7.6Other On-board Supplies

The 2.5 V power rail is derived from the 3.3 V rail using a standard buck converter. This rail is limited to 3 A of current. Vtt for the CPU is derived from the 1.5 V rail using a linear regulator.

2.2.7.7Other Suspend Power

The 5 V suspend is derived from the 12 V suspend using a linear regulator at < 1 A. The 1.8 VSB and 1.5 VSB are derived from the 3.3 V suspend using linear regulators all at < 1 A.

2.2.8IPMC

The MPCBL0010 SBC uses the Renesas* H8S/2168 for the Intelligent Platform Management Controller (IPMC). The IPMC provides a management subsystem for monitoring, event logging, and recovery control. The IPMC serves as the gateway for management applications to access the platform hardware. Some of the key features are:

•Compliant with PICMG 3.0 and IPMI v1.5 rev 1.1

•Automatic rollback capability if an upgrade fails

•Upgradeable from the IPMI KCS interface

•Support for AdvancedMC via IPMB-L

•Supports initiation of a graceful shutdown on the host CPU and ShMC notification insertion and removal.

2.2.9Telecom Clock

The MPCBL0010 SBC supports a telecom clock synchronization circuit. This circuit uses the Zarlink* ZL30410 Multi-Service Line Card PLL and a PLD that act as a clock multiplexer on inputs and outputs. The clock can be synchronized to any of the AdvancedTCA backplane clocks, CLK1A/B and CLK2A/B. Any of the output clocks can be routed to the AdvancedMC CLKA and CLKB signals.

Intel NetStructure® MPCBL0010 Single Board Computer
Technical Product Specification	October 2006
22	Order Number: 304120