Main
Page
Contents
Page
Page
Page
Page
Figures
Tables
Page
Page
Revision History
1.0 Introduction
1.1 Document Organization
1.2 Glossary
Page
2.0 Feature Overview
2.1 Application
2.2 Functional Description
MPCBL0010 SBCFeature Overview
Figure 1. MPCBL0010 Block Diagram
2.2.1 Low Voltage Intel Xeon Processor
6300ESB I/O Controller Hub (ICH)
Intel
2.2.2 Chipset
E7520 Memory Controller Hub (MCH)
2.2.3 Memory (J10, J12)
2.2.4 I/O
2.2.4.1 I/O Controller Hub
2.2.4.2 Real-Time Clock
2.2.4.3 Timers
2.2.4.4 Gigabit Ethernet
2.2.5 AdvancedMC (AMC) Connector (J18, J19)
2.2.6 Firmware Hubs
2.2.6.1 FWH0 (Main BIOS)
2.2.6.2 FWH1 (Backup/Recovery BIOS)
2.2.6.3 Flash ROM Backup Mechanism
2.2.7 Onboard Power Supplies
2.2.7.1 Power Feed Fuses
2.2.7.2 ORing Diodes and Circuit Breaker Protection
2.2.7.3 Isolated -48 V to +12 V, 12 V Suspend, 5 V, 3.3 V Suspend, 1.8 V, and 1.5 V Converters
2.2.7.4 Processor Voltage Regulator Module (VRM)
2.2.8 IPMC
2.2.9 Telecom Clock
2.2.10 AdvancedMC Direct Connect
2.2.11 AdvancedTCA Compliance
3.0 Operating the Unit
3.1 Jumpers
Figure 4. Jumper/Connector Locations
Table 2. Jumper Definitions
3.2 AdvancedMC Filler Panels
3.3 Installing Memory
3.4 Installing and Extracting the SBC
3.4.1 Chassis Installation
3.4.2 Chassis Extraction
Page
3.5 AdvancedMC Module Installation and Extraction
3.6 BIOS Configuration
3.7 Remote Access Configuration
3.8 Software Updates
3.8.1 BIOS Updates
FWH0
FWH1
FWH0
FWH1
Page
3.8.2.4 flashlnx Command Line Options
3.8.3 IPMC Firmware Updates
3.8.3.1 IPMC Firmware Upgrade Using the KCS Interface
3.9 Digital Ground to Chassis Ground Connectivity
4.0 Specifications
4.1 Mechanical Specifications
4.1.1 Board Outline
4.1.2 Backing Plate and Top Cover
4.2 Environmental Specifications
4.3 Reliability Specifications
4.3.1 Mean Time Between Failure (MTBF) Specifications
4.3.1.1 Environmental Assumptions
4.3.1.2 General Assumptions
4.3.1.3 General Notes
4.4 Weight
5.0 Connectors and LEDs
Figure 10. Connector Locations
Table 10. On-board and Backplane Connector Assignments
Page
5.1 Backplane Connectors
5.1.1 Power Distribution Connector (P10)
5.1.2 AdvancedTCA Data Transport Connector (J23)
Page
5.1.3 AdvancedTCA Data Transport Connector (J20)
5.1.4 Alignment Blocks
5.2 On-Board Connectors
5.2.1 POST Code Connector (J13)
5.2.2 Extended IPT700 Debug Port Connector (J25)
5.3 Front Panel Connectors
5.3.1 Ethernet 10/100 Debug Connector (J3)
5.3.2 USB Connector (J4)
5.3.3 Serial Port Connector (J5)
Figure 15. USB Connector (J4)
Table 18. USB Connector (J4) Pin Assignments
Figure 16. Serial Port Connector (J5)
5.3.4 AdvancedMC* Connectors (J18, J19)
Table 20. AdvancedMC* Connector Pin Assignments
5.4 LEDs
Figure 19. Front Panel LEDs (Option 1)
Figure 20. Front Panel B LEDs (Option 2)
Table 21. Front Panel LED Descriptions (Sheet 1 of 2)
5.4.1 POST LED Codes
Table 22. Ethernet 10/100 Debug Connector LED Operation
Table 21. Front Panel LED Descriptions (Sheet 2 of 2)
5.5 Reset Button
6.0 BIOS Features
6.1 Introduction
6.2 BIOS Flash Memory Organization
6.3 Complementary Metal-Oxide Semiconductor (CMOS)
6.4 Redundant BIOS Functionality
6.5 Legacy USB Support
6.5.1 Language Support
6.6 Recovering BIOS Data
6.7 Boot Options
6.7.1 CD-ROM and Network Boot
6.8 Fast Booting Systems
6.8.1 Quick Boot
6.9 BIOS Security Features
6.10 Remote Access Configuration
Table 24. Function Key Escape Code Equivalents (Sheet 2 of 2)
7.0 BIOS Setup
7.1 Introduction
7.2 Main Menu
7.3 Advanced Menu
7.3.1 CPU Configuration Sub-Menu
7.3.2 IDE Configuration Sub-Menu
Page
7.3.2.1 Primary IDE Master/Slave Configuration Options
Tabl e 31 shows the IDE Master/Slave configuration options.
Table 30. IDE Configuration Sub-Menu (Continued)
Table 31. IDE Master/Slave Sub-Menu
7.3.3 SuperIO Configuration Sub-Menu
7.3.4 ACPI Configuration Sub-Menu
7.3.4.1 Advanced ACPI Configuration Sub-Menu
7.3.4.2 Chipset ACPI Configuration Sub-Menu
7.3.5 System Management Sub-Menu
7.3.6 Event Log Configuration Sub-Menu
Table 37. Event Log Configuration Sub-Menu
7.3.6.1 PCI Express Error Masking Configuration Sub-Menu
7.3.7 MPS Configuration Sub-Menu
7.3.8 AdvancedTCA* Channel Routing (PICMG*) Sub-Menu
Tabl e 40 shows MPS Configuration options.
7.3.9 On-board Devices Configuration Sub-Menu
To access this sub-menu, select Advanced on the menu bar, then On-board Devices Configuration.
7.3.10 PCI Express* Configuration Sub-Menu
7.3.11 Remote Access Configuration Sub-Menu
7.3.12 IPMI Configuration Sub-Menu
Page
7.3.13 USB Configuration Sub-Menu
7.3.13.1 USB Mass Storage Device Configuration
Tabl e 48 shows USB Mass Storage Device Configuration options.
7.4 PCIPnP Menu
Table 47. USB Configuration Sub-Menu (Continued)
Table 48. USB Mass Storage Device Configuration
Main Advanced PCIPnP Boot Security Chipset Exit Table 49. PCIPnP Menu
7.5 Boot Menu
7.5.1 Boot Settings Configuration Sub-Menu
7.5.2 Boot Device Priority Sub-Menu
7.5.3 Hard Disk Drives Sub-menu
7.5.4 OS Load Timeout Timer Sub-Menu
7.6 Security Menu
7.7 Chipset Menu
7.7.1 Northbridge Configuration Sub-Menu
7.7.2 Spread Spectrum Clocking Mode Sub-Menu
7.8 Exit Menu
Table 59. Exit Menu (Continued)
8.0 Error Messages
8.1 BIOS Error Messages
8.2 Port 80h POST Codes
Table 61. Bootblock Initialization Code Checkpoints
Table 62. POST Code Checkpoints
Table 62. POST Code Checkpoints (Continued)
Table 63. DIM Code Checkpoints
Table 64. ACPI Runtime Checkpoints
Table 62. POST Code Checkpoints (Continued)
9.0 Addressing
9.1 PCI Configuration Map
Tabl e 65 lists the PCI devices and the bus on which they reside. Table 65. PCI Configuration Map
Page
9.2 FPGA Registers
Table 66. FPGA Register Legend
POST codes are captured in this register as they are written.
POST codes are captured in this register as they are written.
Table 67. FPGA Register Overview
Table 68. POST Codes 00:80h
Table 69. Extended POST Codes 0081h
Page
Page
TXREFx_SEL[2..0]=111
TXREFx_SEL[2..0]=101
Page
Page
9.3 IPMC Addresses
Table 83. IPMC Register Legend (Continued)
Table 84. SBC Control 00h
9.3.0.1 PwrBtn usage
Page
Page
Page
Page
Page
Page
Page
Page
Page
10.0 Hardware Management Overview
10.1 Intelligent Platform Management Controller (IPMC)
Page
10.2 Sensor Data Record (SDR)
Table 109. Hardware Sensors (Sheet 2 of 4)
Table 109. Hardware Sensors (Sheet 3 of 4)
Table 110. OEM Sensor Types
Table 109. Hardware Sensors (Sheet 4 of 4)
10.3 System Event Log (SEL)
Table 111. OEM Event/Reading Type
Table 112. SEL Events Supported (Sheet 1 of 5)
Table 112. SEL Events Supported (Sheet 2 of 5)
Table 112. SEL Events Supported (Sheet 3 of 5)
Table 112. SEL Events Supp orted (Sheet 4 of 5)
Table 112. SEL Events Supported (Sheet 5 of 5)
10.4 IPMB Link Sensor
10.5 Field Replaceable Unit (FRU) Information
10.6 Customizable FRU Area
10.6.1 LinuxCustFru Utility Usage
fileName
-p -v
10.6.2 FRU Customer Area
Page
Page
10.7 E-Keying
10.8 OEM IPMI Commands
10.8.1 Reset BIOS Flash Type
10.8.2 Board Device Channel Port Selection Identifiers
Page
10.8.2.2 GetBoardDeviceChannelPortSelection
This command returns the current device AdvancedTCA channel routing selection.
This command returns the possible selections for the device received in parameters.
10.8.2.3 GetBoardDevicePossibleSelection
Table 117. GetBoardDeviceChannelPortSelection
10.8.3 Set Control State
This command sets the state of a control pin and overrides the control pins auto state.
10.8.4 Get Control State
This command gets the state of a control pin.
10.8.5 Controls Identifier Table
10.9 Hot Swap Process
ICH3
10.9.1 Hot Swap LED
10.10 AdvancedMC Module Activation
10.10.1 Pre-Defined Resources for AdvancedMC Modules
10.11 Temperature and Voltage Sensors
Table 123. Sensors and Thresholds (Version SDR 040)
10.11.1 Processor Events
10.11.2 DIMM Memory Events
10.11.3 System Firmware Progress (POST Error)
10.11.4 Critical Interrupts
10.11.5 System ACPI Power State
10.12 Reset
10.12.1 Warm Reset
10.12.2 Hard Reset
10.13 Field Replaceable Unit (FRU) Information
10.14 IPMC Firmware Code
Page
Page
11.0 Serial Over LAN (SOL)
11.1 References
11.2 SOL Architecture
11.2.1 SOL Implementation
Page
11.2.2 Architectural Components
11.2.2.1 IPMC
11.2.2.2 Ethernet Controller
11.3 Theory of Operation
11.3.1 Front Panel Serial Port or Rear Transition Module
11.4 Serial Over LAN Client
11.5 Reference Configuration Script
11.6 Supported Usage Model
11.6.1 Configuring the Blade for SOL
11.7 Reference Script (reference_cfg) 11.7.1 SOL Configuration Reference Script (reference_cfg)
11.7.2 Default Behavior
11.7.3 SOL User Information
11.7.4 LAN Parameters
11.7.5 SOL Parameters
11.7.6 Channel Parameters
11.7.7 Command Line Options
11.8 Setting up a Serial Over LAN Session
11.8.1 Target Blade Setup
11.8.1.1 BIOS Configuration
11.8.1.2 Operating System Configuration
Page
11.8.1.3 sbcutils RPM Installation
11.8.1.4 Execute the reference_cfg Script
Page
11.8.2 Client Blade Setup
11.8.2.1 Configure the Ethernet Port
11.8.2.2 Installing ipmitool
11.8.2.3 Start an SOL Session
11.8.2.4 Checking SOL Configuration
11.8.2.5 Ending an SOL Session
11.9 Operating Systems for SOL Client (ipmitool)
12.0 Telecom Clock
12.1 Functional Description
12.2 Interface Description
12.2.1 AdvancedTCA Backplane Interface
12.2.2 AdvancedMC Interface
12.2.3 Reset/Interrupt Interface
12.2.4 LPC Interface
12.3.3 Recovered Clock Selection
12.3.4 Configuration
12.3.4.1 Operational Configuration
12.3.5 Alarm Handling
12.4 Telecom Clock API
12.4.1 TRANSMIT CLOCK
12.4.2 Enable/Disable Transmission Clock
12.4.3 Recovered Clock
12.4.4 Automatic Switchover
12.4.5 Automatic Switchover Mode
12.4.6 Select Reference Clock
12.4.7 Reference Frequency for PLL
12.4.8 Primary/Secondary Redundant Clock
12.4.9 Corner Frequency
12.4.10 PLL Operating Mode
12.4.11 Reference Clock Alignment
12.4.12 Hardware Reset
12.4.13 Read Alarm States
12.4.14 Read New Events
12.4.15 Read the Current Reference Clock
12.4.16 sysfs Interface
12.5 Telecom Clock Registers
Page
Page
Page
Page
Page
Table 150. FPGA/PLD Serial Link Bit Definition
13.0 Maintenance
13.1 Supervision
13.2 Diagnostics
13.2.1 In-Target Probe (ITP)
14.0 Thermals
15.0 Component Technology
16.0 Warranty Information
16.1 Intel NetStructure Compute Boards and Platform Products Limited Warranty
16.2 Returning a Defective Product (RMA)
16.3 For the Americas
16.3.1 For Europe, Middle East, and Africa (EMEA)
16.3.2 For Asia and Pacific (APAC)
16.3.3 Limitation of Liability and Remedies
Page
17.0 Customer Support
17.1 Customer Support
17.2 Technical Support and Return for Service Assistance
17.3 Sales Assistance
17.4 Product Code Summary
18.0 Certifications
19.0 Agency InformationClass B
19.1 North America (FCC Class B)
19.3 Japan VCCI Class B
19.2 Canada Industry Canada (ICES-003 Class B) (English and French-translated)
Page
20.0 Safety Warnings
20.1 Mesures de Scurit
20.2 Sicherheitshinweise
20.3 Norme di Sicurezza
20.4 Instrucciones de Seguridad
Page
Appendix A Reference Documents
Page
Appendix B List of Supported Commands (IPMI v1.5 and PICMG 3.0)
Table 153. IPMI 1.5 Supported Commands (Sheet 1 of 2)
Table 153. IPMI 1.5 Supported Commands (Sheet 2 of 2)
Table 154. PICMG 3.0 IPMI Supported Commands
