
UART: UART override;
when set, the serial port to the IPMC will
when cleared, the IPMC will receive the data (RX) for monitoring purposes but will not be able to transmit
LTYPE: LED type.
when cleared, whenever possible, amber LEDs are used instead of red. when set, red is used instead of amber.
Applicable LEDs: Postcode/HardDisk/Debug LED.
PwrBtn: ICH Power Button Control. This bit can be set, but it cannot be cleared. It will clear itself when the power sequencing requested is completed (i.e. TurnX=0).
Note: This bit should only be set when TurnX is 0. This bit will not work when a
TurnX: Turn ON or turn OFF in progress.
BoardON: Power status of the board 1 = Board ON
HTU: Hard
On a Read, this will always return 0.
9.3.0.1PwrBtn usage
For a power up:
1.IPMC sets bit PowerBtn
2.FPGA asserts PowerBtn ICH input and waits for the ICH to
3.When "suspend" is
For a power down:
1.IPMC sets bit PowerBtn
2.FPGA asserts PowerBtn for 33 ms (ICH debouncer delay is 16 ms)
3.FPGA waits for the ICH "suspend" output to be
Note: There is no timeout and if the operating system does not shut down, the board remains stuck in this condition.
The IPMC must implement a timeout of reasonable length (i.e. seconds) and perform a hard
Quick
1.IPMC sets bit HTO.
2.FPGA turns off all supplies.
Note: The “suspend” information from the chipset does not reflect the state of the power supply.
| Intel NetStructure® MPCBL0010 Single Board Computer |
October 2006 | Technical Product Specification |
Order Number: 304120 | 105 |