Intel MPCBL0010 Hardware Management Overview, Intelligent Platform Management Controller Ipmc

Hardware Management Overview—MPCBL0010 SBC

10.0Hardware Management Overview

10.1Intelligent Platform Management Controller (IPMC)

The MPCBL0010 SBC uses the Renesas* H8S/2168 for the Intelligent Platform Management Controller (IPMC). The IPMC management subsystem provides monitoring, event logging, and recovery control. The IPMC serves as the gateway for management applications to access the platform hardware.

The main processors communicate with the IPMC using the Keyboard Controller Style (KCS) interface. BIOS uses the SMM interface. The base address of the LPC interface for SMS is 0xCA2 and 0xCA4 for SMM operation. The BIOS is also able to communicate with the IPMC for POST error logging purposes and fault resilient purposes.

The memory subsystem of the IPMC consists of integrated flash memory to hold the IPMC operation code, and integrated RAM for data. The field replacement unit (FRU) inventory information is stored in the nonvolatile memory on an EEPROM connected via a local I2C interface to the IPMC microcontroller. It is possible to store up to 4 KB within the FRU inventory information stored in the EEPROM. Events are generated over the IPMB to the Shelf Manager (ShMC), which maintains a SEL for each device in the chassis. This ensures that ‘postmortem’ logging information is available even if the main processor for the MPCBL0010 SBC becomes disabled or non-functional.

The IPMC provides six I2C bus connections. Two are used as the redundant IPMB connections to the backplane, one is used for IPMB-L bus with AdvancedMC* modules, two are used for the LAN connections for IPMI Over LAN, and the last one is for local EEPROM storage.

	Intel NetStructure® MPCBL0010 Single Board Computer
October 2006	Technical Product Specification
Order Number: 304120	115