Intel 80286, 80287 manual Chapter Memory Management and Virtual Addressing, Table of Contents

TABLE OF CONTENTS

	Page
Reserved and Dedicated Interrupt Vectors	5-5
System Initialization	5-7
CHAPTER 6
MEMORY MANAGEMENT AND VIRTUAL ADDRESSING
Memory Management Overview	6-1
Virtual Addresses	6-2
Descriptor Tables	6-4
Virtual-to-Physical Address Translation	6-6
Segments and Segment Descriptors	6-7
Memory Management Registers	6-9
Segment Address Translation Registers	6-9
System Address Registers	6-12
CHAPTER 7
PROTECTION
Introduction	7-1
Types of Protection	7-1
Protection Implementation	7-2
Memory Management and Protection	7-4
Separation of Address Spaces	7-5
LDT and GDT Access Checks	7-5
Type Validation	7-6
Privilege Levels and Protection	7-8
Example of Using Four Privilege Levels	7-8
Privilege Usage	7-9
Segment Descriptor	7-10
Data Accesses	7-12
Code Segment Access	7-13
Data Access Restriction by Privilege Level	7-13
POinter Privilege Stamping via ARPL	7-14
Control Transfers	7-15
Gates	7-16
Call Gates	7-17
Intra-Level Transfers via Call Gate	7-18
Inter-Level Control Transfer via Call Gates	7-19
Stack Changes Caused by Call Gates	7-20
Inter-Level Returns	7-20
CHAPTERS
TASKS AND STATE TRANSITIONS
Introduction	8-1
Task State Segments and Descriptors	8-1
Task State Segment Descriptors	8-3
Task Switching	8·4
Task Linking	8-7
Task Gates	8-8
CHAPTER 9
INTERRUPTS AND EXCEPTIONS
Interrupt Descriptor Table	9-1
Hardware Initiated Interrupts	9-2

vii