Intel 80286, 80287 manual Chapter Real Address Mode, Addressing and Segmentation

CHAPTER 5

REAL ADDRESS MODE

The 80286 can be operated in either of two modes according to the status of the Protection Enabled bit of the MSW status register. In contrast to the "modes" and "mode bits" <if some processors, however, the 80286 modes do not represent a radical transition between conflicting architectures. Instead, the setting of the Protection Enabled bit simply determines whether certain advanced features, in addition to the baseline architecture of the 80286, are to be made available to system designers and programmers.

If the Protection Enabled (PE) bit is set by the programmer, the processor changes into Protected Virtual Address Mode. In this mode of operation, memory addressing is performed in terms of virtual addresses, with on-chip mapping mechanisms performing the virtual-to-physical translation. Only in this mode can the system designer make use of the advanced architectural features of the 80286: virtual memory support, system-wide protection, and built-in multitasking mechanisms are among the new features provided in this mode of operation. Refer to Part II of this book (Chapters 6 through 11) for details on Protected Mode operation.

Initially, upon system reset, the processor starts up in Real Address Mode. In this mode of operation, all memory addressing is performed in terms of real physical addresses. In effect, the architecture of the 80286 in this mode is identical to that of the 8086 and other processors in the 8086 family. The principal features of this baseline architecture have already been discussed throughout Part I (Chapters 2 through 4) of this book. This chapter discusses certain additional topics-addressing, interrupt handling, and system initialization-that complete the system programmer's view of the 80286 in Real Address Mode.

5.1 ADDRESSING AND SEGMENTATION

Like other processors in the 8086 family, the 80286 provides a one-megabyte memory space (220 bytes) when operated in Real Address Mode. Physical addresses are the 20-bit values that uniquely identify each byte location in this address space. Physical addresses, therefore, may range from 0 through FFFFFH. Address bits A20-A23 may not always be zero in Real Address Mode. A20-A23 should not be used by the system while the 80286 is operating in Real Address Mode. I

An address is specified by a 32-bit pointer containing two components: (1) a I6-bit effective address offset that determines the displacement, in bytes, of a particular location within a segment; and (2) a I6-bit segment selector component that determines the starting address of the segment. Both compo- nents of an address may be referenced explicitly by an instruction (such as JMP, LES, LDS, or CALL); more often, however, the segment selector is simply the contents of a segment register.

The interpretation of the first component, the effective address offset, is straight-forward. Segments are at most 64K (216) bytes in length, so an unsigned I6-bit quantity is sufficient to address any arbitrary byte location with a segment. The lowest"addressed byte within a segment has an offset of 0, and the highest-addressed byte has an offset of FFFFH. Data operands must be completely contained within a segment and must be contiguous. (These rules apply in both modes.)

A segment selector is the second component of a logical address. This I6-bit quantity specifies the starting address of a segment within a physical address space of 220 bytes.

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