Intel 80286, 80287 manual System Initialization, Processor State after Reset, Flags, MSW Fffoh

REAL ADDRESS MODE

INTO Detected Overflow (Interrupt 4). Execution of the INTO conditional software interrupt instruction will cause this interrupt to occur if the overflow bit (OF) of the FLAGS register is set. The saved value of CS:IP will point to the next instruction.

BOUND Range Exceeded (Interrupt 5). Execution of the BOUND instruction will cause this interrupt to occur if the specified array index is found to be invalid with respect to the given array bounds. The saved value of CS:IP will point to the first byte of the BOUND instruction.

Invalid Opcode (Interrupt 6). This exception will occur if execution of an invalid opcode is attempted. (In Real Address Mode, most of the Protected Virtual Address Mode instructions are classified as invalid and should not be used). This interrupt can also occur if the effective address given by certain instructions, notably BOUND, LDS, LES, and LIDT, specifies a register rather than a memory location. The saved value of CS:IP will point to the first byte of the invalid instruction or opcode.

Processor Extension Not Available (Interrupt 7). Execution of the ESC instruction will cause this interrupt to occur if the status bits of the MSW indicate that processor extension functions are to be emulated in software. Refer to section 10.2.2 for more details. The saved value of CS:IP will point to the first byte of the ESC or the WAIT instruction.

Interrupt Table Limit Too Small (Interrupt 8). This interrupt will occur if the limit of the inter- rupt vector table was changed from 3FFH by the LIDT instruction and an interrupt whose vector is outside the limit occurs. The saved value of CS:IP will point to the first byte of the instruction that caused the interrupt or that was ready to execute before an external interrupt occurred. No error code is pushed.

Processor Extension Segment Overrun Interrupt (Interrupt 9). The interrupt will occur if a processor extension memory operand does not fit in a segment. The saved CS:IP will point at the first byte of the instruction that caused the interrupt.

Segment Overrun Exception (Interrupt 13). This interrupt will occur if a memory operand does not fit in a segment. In Real Mode this will occur only when a word operand begins at segment offset OFFFFH. The saved CS:IP will point at the first byte of the instruction that caused the interrupt. No error code is pushed.

Processor Extension Error (Interrupt 16). Thisinterrupt occurs after the numeric instruction that caused the error. It can only occur while executing a subsequent WAIT or ESC. The saved value of CS:IP will point to the first byte of the ESC or the WAIT instruction. The address of the failed numeric instruction is saved in the NPX.

5.3SYSTEM INITIALIZATION

The 80286 provides an orderly way to start or restart an executing system. Upon receipt of the RESET signal, certain processor registers go into the determinate state shown in table 5-3.

Table 5-3. Processor State after RESET

Register	Contents
FLAGS	0002 (H)
MSW	FFFO(H)
IP	FFFO (H)
CS	FOOD (H)
DS	0000 (H)
SS	0000 (H)
ES	0000 (H)

5-7