Intel 80287, 80286 manual ~,m~

Models: 80287 80286

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MEMORY MANAGEMENT AND VIRTUAL ADDRESSING,

SEGMENT ADDRESS TRANSLATION REGISTERS

16-BIT

48-BIT HIDDEN DESCRIPTOR CACHE

 

 

 

 

 

 

I,~_,m''''~'"

 

 

 

 

 

 

DATA SEGMENT REGISTER

 

 

 

 

 

 

EXTRA SEGMENT REGISTER

 

 

 

 

 

 

STACK SEGMENT REGISTER

 

63

48 47

4039

16 15

0

 

 

ACCESS

SEGMENT BASE

SEGMENT

 

 

 

RIGHTS

ADDRESS

SIZE

 

SYSTEM ADDRESS REGISTERS

 

 

 

 

GDTR

II------------t------,IGLOBAL DESCRIPTOR TABLE REGISTER

 

 

40 BIT EXPLICIT REGISTER

 

 

IDTR _

 

 

 

INTERRUPT DESCRIPTOR TABLE REGISTER

 

39

 

 

16 15

o

 

 

 

BASE

 

LIMIT

 

 

 

16-BIT VISIBLE

 

40-BIT HIDDEN DESCRIPTOR CACHE

ILOCAL DESCRIPTOR TABLE REGISTER

 

SELECTOR

(AUTOMATICALLY LOADED FROM LDTR WITHIN GDT)

 

L5-5--------4-0~3-9------------------1-6~1~5----------~0

 

 

 

 

BASE

LIMIT

 

G30108

Figure 6-8. Memory Management Registers

The operations that load these registers-or, more exactly, those that load the visible portion of these

registers-arc normal program instructions. These instructions may be divided into two categories:

I, Direct segment-register load instructions_ These instructions (such as LDS, LES, MOV, POP,

etc.) can explicitly reference the SS, DS, or ES segment registers as the destination operand_

2.Implied segment-register load instructions. These instructions (such as intersegment CALL and JMP) implicitly reference the CS code segment register; as a result of these operations, the contents of CS are altered.

Using these instructions, a program loads ine visiul~ pal i (If the s6giTierll register 'v',:ithu16-bit ~ele~tGr

(i.e., the high-order word of a virtual address pointer). Whenever this is done, the processor automati- cally uses the selector to reference the appropriate descriptor and loads the 48-bit hidden descriptor cache for that segment register.

The correspondence between selectors and descriptors has already been described. Remember that the selector's TI bit indicates one of the two descriptor tables, either the LDT or the GDT. Within the indicated table, a particular entry is chosen by the selector's 13-bit INDEX field. This index, scaled by a factor of 8, represents the relative displacement of the chosen table entry (a descriptor).

6-10

Page 120
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Intel 80287, 80286 manual ~,m~