Intel 80286 manual Appendix B Compatibility Between, 80287 NPX

APPENDIX B

COMPATIBILITY BETWEEN

THE 80287 NPX AND THE 8087

The 80286/80287 operating in Real-Address mode will execute 8087 programs without major modifi- cation. However, because of differences in the handling of numeric exceptions by the 80287 NPX and the 8087 NPX, exception-handling routines may need to be changed.

This appendix summarizes the differences between the 80287 NPX and the 8087 NPX, and provides details showing how 8087 programs can be ported to the 80287.

1.The 80287 signals exceptions through a dedicated ERROR line to the 80286. The 80287 error signal does not pass through an interrupt controller (the 8087 INT signal does). Therefore, any interrupt-controller-oriented instructions in numeric exception handlers for the 8087 should be deleted.

2.The 8087 instructions FENI/FNENI and FDISI/FNDISI perform no useful function in the 80287. If the 80287 encounters one of these opcodes in its instruction stream, the instruction will effec- tively be ignored-none of the 80287 internal states will be updated. While 8087 code containing these instructions may be executed on the 80287, it is unlikely that the exception-handling routines containing these instructions will be completely portable to the 80287.

3.Interrupt vector 16 must point to the numeric exception handling routine.

4.The ESC instruction address saved in the 80287 includes any leading prefixes before the ESC opcode. The corresponding address saved in the 8087 does not include leading prefixes.

S.In Protected-Address mode, the format of the 80287's saved instruction and address pointers is different than for the 8087. The instruction opcode is not saved in Protected mode-exception handlers will have to retrieve the opcode from memory if needed.

6.Interrupt 7 will occur in the 80286 when executing ESC instructions with either TS (task switched) or EM (emulation) of the 80286 MSW set (TS = 1 or EM = 1). If TS is set, then a WAIT instruc- tion will also cause interrupt 7. An exception handler should be included in 80287 code to handle these situations.

7.Interrupt 9 will occur if the second or subsequent words of a floating-point operand fall outside a segment's size. Interrupt 13 will occur if the starting address of a numeric operand falls outside a segment's size. An exception handler should be included in 80287 code to report these program- ming errors.

8.Except for the processor control instructions, all of the 80287 numeric instructions are automati- cally synchronized by the 80286 CPU-the 80286 automatically tests the BUSY line from the 80287 to ensure that the 80287 has completed its previous instruction before executing the next ESC instruction. No explicit W1AIT instructions are required to assure this synchronization. For the 8087 used with 8086 and 8088 processors, explicit WAITs are required before each numeric instruction to ensure synchronization. Although 8087 programs having explicit WAIT instructions will execute perfectly on the 80287 without reassembly, these WAIT instructions are unnecessary.

9.Since the 80287 does not require WAIT instructions before each numeric instruction, the ASM286 assembler does not automatically generate these WAIT instructions. The ASM86 assembler, however, automatically precedes every ESC instruction with a WAIT instruction. Although numeric routines generated using the ASM86 assembler will generally execute correctly on the 80286/20, reassembly using ASM286 may result in a more compact code image.

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