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Intel 80287, 80286 manual Machine Instruction Encoding and Decoding

Models: 80287 80286

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MACHINE INSTRUCTION ENCODING AND DECODING

P:0 = do not pop stack

1 = pop stack after operation

REG: register stack element 000 = stack top

001 = next on stack

010 = third stack element, etc.

Table A-2 lists all 80287 machine instructions in binary sequence. This table may be used to "disassem- ble" instructions in unformatted memory dumps or instructions monitored from the data bus. Users writing exception handlers may also find this information useful to identify the offending instruction.

Table A·2. Machine Instruction Decodin.9 Guide

	1st Byte
Hex	Binary		2nd Byte
Hex	Binary
08	1101	1000	MOOOO OR/M
08	1101	1000	MOOOO 1R/M
08	1101	1000	M0001	OR/M
08	1101	1000	M0001	1R/M
08	1101	1000	M0010 OR/M
08	1101	1000	M0010 1R/M
08	1101	1000	M0011	OR/M
08	1101	1000	M0011	1R/M
08	1101	1000	1100	OREG
08	1101	1000	1100	1REG
08	1101	1000	1101	OREG
08	1101	1000	1101	1REG
08	1101	1000	1110	OREG
08	1101	1000	1110	1REG
08	1101	1000	1111	OREG
08	1101	1000	1111	1REG
09	1101	1001	MOOOO OR/M
09	1101	1001	MOOOO 1R/M
09	1101	1001	M0001	OR/M
09	1101	1001	M0001	1R/M
09	1101	1001	M0010 OR/M
09	1101	1001	M0010 1R/M
09	1101	1001	M0011	OR/M
09	1101	1001	M0011	1R/M
09	1101	1001	1100	OREG
09	1101	1001	1100	1REG
09	1101	1001	1101	0000
09	1101	1001	1101	0001
09	1101	1001	1101	001-
09	1101	1001	1101	01--
D9	1101	1001	1101	1RFG
09	1101	1001	1110	0000
09	1101	1001	1110	0001
09	1101	1001	1110	001·
09	1101	1001	1110	0100
09	1101	1001	1110	0101
09	1101	1001	1110	011·
09	1101	1001	1110	1000

Bytes 3,4	ASM286 Instruction
Bytes 3,4		Format
		Format
(disp-Io),(disp-hi)	FAOO	short-real
(disp-Io),(disp-hi)	FMUL	short-real
(disp-Io),(disp-hi)	FCOM	short-real
(disp-Io),(disp-hi)	FCOMP	short-real
(disp-Io),(disp-hi)	FSUB	short-real
(disp-Io),(disp-hi)	FSUBR	short-real
(disp-Io),(disp-hi)	FOIV	short-real
(disp-Io),(disp-hi)	FOIVR	short-real
	FAOO	ST,ST(i)
	FMUL	ST,ST(i)
	FCOM	ST(i)
	FCOMP	ST(i)
	FSUB	ST,ST(i)
	FSUBR	ST,ST(i)
	FOIV	ST,ST(i)
	FOIVR	ST,ST(i)
(disp-Io),(disp-hi)	FLO	short-real
	reserved
(disp-Io),(disp-hi)	FST	short-real
(disp-Io),(disp-hi)	FSTP	short-real
(disp-Io),(disp-hi)	FLOENV 14-bytes
(disp-Io),(disp-hi)	FLOCW	2-bytes
(disp-Io),(disp-hi)	~ FSTENV 14-bytes
(disp-Io),(disp-hi)	FSTCW	2-bytes
	FLO	ST(i)
	FXCH	ST(i)
	FNOP

reserved reserved reserved *(1 )

FCHS

FABS reserved

FTST

FXAM reserved FL01

A-2

Image 484

Intel 80287, 80286 manual Machine Instruction Encoding and Decoding, Table A·2. Machine Instruction Decodin.9 Guide

Contents

Page ··PRICEIN Order Number DollarsInfef Call Toll Free 800 548-4725for phone ordersCustomer Support 80287 Programmers Reference Manual @INTELCORPORATION Preface Organization of this ManualPage Table of Contents Real Address Mode Extended Instruction SETTable of Contents Chapter Memory Management and Virtual Addressing10-1 10-310-4 10-5Flag Word Contents 80286/80287 Supported Data TypesCode and Data Segments Assigned to a Privilege Level Dynamic Segment Relocation and Expansion of Segment LimitReserved Exceptions and Interrupts Inter Introduction to Page Chapter Introduction to Modes of Operation Advanced FeaturesMemory Management Task Management Protection MechanismsSupport for Operating Systems Organization of this BookRelated Publications Inter Base Architecture Page Chapter Base Architecture Memory Organization and Segmentation8000 r Bytes and Words in Memory Ascii Base Architecture ·3 /80287 Supported Data TypesBase Architecture Registers General RegistersMemory Segmentation and Segment Registers Real Address Mode Segment Selector Interpretation Index, Pointer, and Base RegistersInlel Inter Stack Operation BP Usage as a Stack Frame Base Pointer Status and Control Registers Implied Segment Usage by Index, Pointer, and Base Registers10. Flags Register Addressing Modes OperandsRegister and Immediate Modes Memory Addressing ModesSegment Selection EASE Architecture Segment Register Selection Rules Offset ComputationPRog~~~D Memory Operand AddressingModes INPUT/OUTPUTBX, 51 13. Complex Addressing Modes AL,FE OUTOUT FF,AL Interrupts and Exceptions Hierarchy of Instruction Sets Interrupt Vector Assignments Real Address Mode 80186~80188 Page Basic Instruction Set Page Data Movement Instructions General-Purpose Data Movement InstructionsStack Manipulation Instructions PushBasic Instruction SET Flag Operation with the Basic Instruction SET Status FlagsControl Flags Hm====iArithmetic Instructions Previous Push Instructions LOW Address After Before PopaBasic Instruction SET Addition Instructions Subtraction InstructionsMultiplication Instructions Logical Instructions Division InstructionsBoolean Operation Instructions Shift and Rotate Instructions Wordoprnd~-i 01, I, I aI a1,1, I, I, I a1,1,1, I aI alaiI 10 01, ,1,101, 0101,1, 01 0 10 I 1I 1I 0 1I 1 1I o I o I 1 o I 1I 1111010rrG Ll 1 1 1 l 1 Test and Compare Instructions Type Conversion and No-Operation InstructionsControl Transfer Instructions Unconditional Transfer Instructions Call Instruction Conditional Transfer Instructions JG/JNLE JGE/JNLJL/JNGE JLE/JNGSoftware-Generated Interrupts Translate Instruction Character Translation and String InstructionsString Manipulation Instructions and Repeat Prefixes String Movement Instructions Address Manipulation Instructions Intel Flag Control InstructionsFlag Transfer Instructions Unpacked BCD Adjustment Instructions Packed BCD Adjustment InstructionsBINARY-CODED Decimal Arithmetic Instructions Trusted and Privileged Restrictions on Popf and Iret Trusted InstructionsMachine State Instructions Input and Output Instructions Processor Extension InstructionsProcessor Extension Synchronization Instructions Numeric Data Processor InstructionsBasic Instruction SET Data Transfer Instructions Page Extended Instruction Set Page Chapter Extended Instruction SET Block 1/0 InstructionsHIGH-LEVEL Instructions Formal Definition of the Enter Instruction Variable Access in Nested Procedures Extended Instruction SET2b. Stack Frame for Procedure a 2d. Stack Frame for Procedure C at Level 3 Called from B Extended Instruction SET Page Real Address Mode Page Chapter Real Address Mode Addressing and SegmentationReal Address Mode Real Address Mode Overlapping Segments to Save Physical MemoryNMI Interrupt PrioritiesIntr Interrupt Procedures Reserved and Dedicated Interrupt VectorsESC Processor State after Reset System InitializationFlags MSW FffohReal Address Mode ·Memory Management Virtual Addressing Page Chapter Memory Management and Virtual Addressing Memory Management OverviewVirtual Addresses Format of the Segment Selector ComponentAddress Spaces and Task Isolation Descriptor Tables PiDPll~1 PIDPLI~1 VIRTUAL-TO-PHYSICAL Address TranslationSegments and Segment Descriptors LOT DescriptorVirtual-to-Physical Address Translation Memory Management Registers Segment Address Translation Registers~,m~ =--=--=1~~ System Address Registers Memory Management and Virtual Addressing Page Protection7 Page Chapter Protection Protection Implementation Addressing Segments of a Module within a Task Protection Descriptor Cache RegistersLOT and GOT Access Checks Separation of Address SpacesLJol LIT Example of Using Four Privilege Levels Privilege Levels and ProtectionPrivilege Usage Segment Descriptor DPL ~~~/do I I LJ. ITI~~Data Accesses Code Segment Access Data Access Restriction by Privilege LevelPointer Privilege Stamping via Arpl Control Transfers NTE RGates 10. Gate Descriptor Format Call Gates Call Gate Checks INTRA-LEVEL Transfers VIA Call GateSe!eC!0r j ,,It Niiii INTER-LEVEL Control Transfer VIA Call Gates Protection Stack Changes Caused by Call Gates 12. Stack Contents after an Inter-Level Call Inter-Level Return Checks Tasks and State Transitions Page Introduction Task State Segments and DescriptorsTasks and State Transitions Task State Segment and TSS RegistersTask State Segment Descriptors Task Switching I01Tasks and State Transitions Checks Made during a Task Switch Task Linking CALL/INT IretTask Gates Task Gate Descriptor~ASK Page Interrupts and Exceptions Page Interrupt Descriptor Table Interrupt Descriptor Table DefinitionHardware Initiated Interrupts An eve.! eXtern8~.~~t~~pr~~~~~1Software Initiated Interrupts Interrupt Gates and Trap GatesTrap/Interrupt Gate Descriptors SSFROMTSS--~.~r~------~l Interrupts and Exceptions Trap and Interrupt Gate ChecksInfer Interrupt and Gate InteractionsScheduling Considerations Deciding Between Task, Trap, and Interrupt GatesProtection Exceptions and Reserved Vectors Invalid OP-Code Interrupt Double Fault InterruptProcessor Extension Segment Overrun Interrupt Invalid Task State Segment Interrupt Not Present InterruptStack Fault Interrupt Conditions That Invalidate the TSSGeneral Protection Fault Interrupt Additional Exceptions and InterruptsSingle Step Interrupt Interrupt IDTSystem Control Initialization Page Chapter System Control and Initialization Descriptor Table Registers.·System Control and Initialization Local and Global Descriptor Table DefinitionSystem Control Instructions Machine Status Word MSW Bit FunctionsWait ESCIfTS=1 Initialization 03FFHReal Address Mode 10-8 Advanced Topics Page Special Segment Attributes Virtual Memory ManagementConforming Code Segments Expand-Down Data Segments Expand-Down SegmentPointer Validation Dynamic Segment Relocation and Expansion of Segment limitPointer Integrity RPL and the Trojan Horse Problem Descriptor ValidationNPX Context Switching Multiprocessor ConsiderationsExample of NPX Context Switching Advanced TopicsShutdown Page Appendix System Initialization Page Appendix a System Initialization System Initialization System .INITIALIZATION System Initialization Ax,.x Intel· Mov!w MovSiW AX,cl Page Appendix 80286 Instruction Set Page Appendix B 80286 Instruction SET 80286 Instruction SET Figure B-1. In Instruction Byte FormatRb = Rw = REG =Mod=OO Mod=01 Mod=10 Mod=11 BX + D8 SI +80286 U\lSTRUCTION SET Figure B-2 Ir Instruction Byte FormatInstruction Description ClocksFlags Modified Protected Mode Exceptions Real Address Mode ExceptionsError Codes Flags Undefined#UD #NM#DF #MP#MF 16 Math Fault No Error Code #GP 13 General Protection Selector or Zero Error Code#MP 9 Math Unit Protection Fault No Error Code #NM 7 No Math Unit Available No Error Code #NP 11 Not Present Selector Error Code#SS 12 Stack Fault Selector or Zero Error Code #TS 10 Invalid Task State Segment Selector Error CodePrivilege Level and Task Switching on #UD 6 Undefined Opcode No Error CodeSwitchtasks 80286 Instruction SET 80286 Instruction SET AAA Ascii Adjust AL After Addition AAD Ascii Adjust AX Before Division AAOD4 OA AAMAAS-ASCII Adjust AL After Subtraction AASADC ADC/ ADD-Integer AdditionADD AND-Logical ARPL- Adjust RPL Field of Selector BOUND-Check Array Index Against Bounds Bound rw,md noj=13Flags Modified Flags UndefinedOperation CallCall FAR Call Conforming Code SegmentCall Nonconforming Code Segment Call to Call GateProtected Mode Exceptions 80286 Instruction SET Call Gate to More PrivilegeCall Gate to Same Privilege Call Task GateInterrupt l3 for a word operand at offset Offffh Caw-Convert Byte into Word C8WCLC-Clear Carry Flag CLCCLD-Clear Direction Flag CLOProtected Mode Exceptions Real Address Mode ExceptionsEll-Clear Interrupt Flag 80286·INSTRUCTION SETCLTS-Clear Task Switched Flag Opcode Instruction ClocksDescriptionCMC-Complement Carry Flag CMCCMP-Compare Two Operands CMPCMPS8 CmpswCWO-Convert Word to Doubleword CWDDAA-Decimal Adjust AL After Addition DAADAS-Decimal Adjust AL After Subtraction DEC-Decrement by Opcode Structlon Clocks DescriptionDIVeb DIV -Unsigned DivideDIVew ENTER-Make Stack Frame for Procedure Parameters BP= Frameptr80286 Instruction SET Protected Mode Exceptions HLT-Halt IDIV-Signed Divide IMUL-Signed Multiply Opcode Instruction Clocks Description Imul eb21,mem=24 Signed multiply rw = 21,mem=24 Signed multiply rw = EA word X imm. byteIN-Input from Port INC Mem=7 Increment EA word byINS/INSB/INSW-Input from Port to String INSInsb InswINT IINTO-Call to Interrupt Procedure INT3Interrupt to Inner Privilege InterruptInterrupt to Same Privilege Level #GP, #NP, #SS, and #TS, as indicated in the list above IRET-Interrupt Return Opcode Instruction Clock DescriptionIret Interrupt ReturnInterrupt Return on Stack Interrupt Return to Same Level#GP, #NP, or #88, as indicated in the above listing JAE JBEJGE JLE80286 Instruction SET JMP-Jump Jump FAR Jump Conforming Code SegmentJump Nonconforming Code Segment Jump to Call GateJump Task State Segment LAHF-load Flags into AH Register Lahf14,mem=16 Load highrw= Access Rights byte, selector ew Real Address Mode ExceptionInstruction SET 02 IrLDS LOS/ LES-Load Doubleword PointerLES 80286 Instruction SET Protected Mode Exceptions LEA-load Effective Address OffsetLEAVE-HighLevel Procedure Exit LeaveLGDTILIDT-Load Global/Interrupt Descriptor Table Register LgdtLoad m into Global Descriptor Table reg LlDTLLDT-Load Local Descriptor Table Register Lldt ewLoad selector ew into Local Descriptor Table RegisterLMSW-Load Machine Status Word 01 /6 LMSWew Mem=6LOCK-AssertBUS Lock Signal LockLODS8 LodsLodsw LOOP/LOOPcond-Loop Control with CX Counter LSL-LoadSegment Limit 14,mem=16 Load rw = Segment Limit, selector ewLTR-Load Task Register 00 /3 LTR ew 17,mem=19Opcode Instruction Clocks Description Mem=3 Move byte register into EA byteMem=3 Move word register into EA word Mem=5 Move EA byte into byte registerInterrupt 13 for a word operand at offset Offffh MOVS/MOVSB/MOVSW-Move Data from String to String MovsMOVS8 MovswMUL-Unsigned Multiplication of AL or AX NEG eb NEG-TwosComplement NegationNEG ew NOP-No Operation NOT-OnesComplement Negation NotOR- Logical Inclusive or OUT OX,AL Output byte AL to port number OXOUT OX,AX Output word AX to port number OXOutsb OutsOutsw POP POP SSInter FlAGS Undefined PopaPOPF-Pop from Stack into the Flags Register PopfPUSH-Push a Word onto the Stack PushPush CS Push SSPUSHA-Push All General Registers Push flag~ register PUSHF-Push Flags Register onto the StackPushf RCL RCRROL RORInterrupt 13 for a word operand at offset Offffh REP INS REP InsbREP Insw REP Movs80286 Instruction SET RET -Return from Procedure RETReturn to Same Level Return to Outer Privilege LevelSahf -Store AH into Flags SahfSAR SALSHR Interrupt 13 for a word operand at offset Offffh SBB-Integer Subtraction With Borrow SBBSCAS/SCASB/SCASW-Compare String Data Sgdt /SIDT-Store Global/Interrupt Descriptor Table Register 101SLOT-Store Local Descriptor Table Register Smsw -Store Machine Status Word 103STe-SetCarry Flag 104STOSetDirection Flag STOSTI-Set Interrupt Enable Flag STIStoss Stosw00 /1 STR ew Mem=3 STR-Store Task Register108 SUB-Integer Subtraction SUBTEST-Logical Compare TestVERR,VERW-Verifya Segment for Reading or Writing 14,mem=16 Set ZF=1 if seg. can be read, selector ew14,mem=16 111112 WAIT-Wait Until Busy Pin Is Inactive High WaitXCHG- Exchange Memory/Register with Register XchgXlat -Table Look-up Translation Xlat mb Set AL to memory byte Osbx + unsignedXlatb 115XOR-Logical Exclusive or XORAppendix 8086/8088 Compatibility Considerations Page Software Compatibility Considerations Table C-1. New 80286 InterruptsPushbp MOVBP,SP XCHGBP,BP Hardware Compatibility Considerations Page 80286/80386 Software Page 80286/80386 Softvvare 80286/80386 Software Compatibility Considerations Index Index-1Index-2 Index-3 LODS/LODSB/LODSW, 3-24, B-69 Index-4Index-5 Index-6 Numeric Processor Extension NPX Page AN Introduction to 80286 MicrosystemOrganization of This Manual Related PublicationsChapter Overview of Numeric Processing Unnormals-Descendents of Denormal OperandsChapter SYSTEM-LEVEL Numeric Programming Glossary of 80287 and FLOATING-POINT Terminology Index 80287Tables Storage Allocation DirectivesOverview of Numeric Processing Page Introduction to the 80287 Numeric Processor Extension PerformanceOverview of Numeric Processing Fxam StackO assumed ExamineApplications ± Vb2 4acUpgradability Programming Interface PASCAL-286 FORTRAN-286Hardware Interface Numeric Data Types~r=~=~ Numeric Processor Architecture NPX Register StackNPX Status Word 80287 Register SetControl Word Status WordInfinity, positive Inter Tag Word Format Computation Fundamentals Number SystemData Types and Formats Number SystemData Formats Binary Integers Rounding Control Precision Control ·6. Rounding ModesSpecial Computational Situations Special Numeric ValuesNonnormal Real Numbers Denormalization Process Overview of Numeric ProcessingUnnormals-Descendents of Denormal Operands Frndint FsqrtFIST, FISTP, Fbstp FLDInfinity FLD, FBLD1 FILD2 FST,FSTP Fbstp FIST, FistpFprem Fsqrt+co Fxtract FrndintFtst Largest SmallestZero Smallest ......1 ---- 15 bits-----l..~1U U2 ZeroU U Bits Class NaNs 16. Temporary Real Encodings Sign Biased ExponentSignificand· NormalsInvalid Operation 16. Temporary Real Encodings ContdZero Divisor Overview of Numeric Processing Denormalized Operand 17. Exception Conditions and Masked Responses 17. Exception Conditions and Masked Responses Contd Masked response to overflow exception earlier11. Arithmetic Example Using Infinity Software Exception Handling Programming Numeric Applications Page Compatibility with the 8087 NPX 80287 NPX Instruction SETNumeric Operands FAD D destination, source Data Transfer InstructionsProgramming Numeric Applications Arithmetic Instructions Arithmetic Instructions Fadd FsubFmulp Fdiv AzimuthFsubrp / /destination/source Fprem Condition Code Interpretation after Fprem Programming Numeric Applications Fabs Fcom / /sourceComparison Instructions Condition Code Interpretation after FcomFcompp FxamFptan STO 1rFpatan F2XM1FYL2X FYL2XP1Constant Instructions Processor Control Instructions Finitifninit Fstsw AX/FNSTSW AX FSAVE/FRSTOR Memory Layout Fstenvifldenv Memory Layout Ffree destination Programming Numeric Applications 12. Key to Operand TypesInstruction Execution Time 13. Execution Penalties Instruction Length ·14. Instruction Set Reference Data 14. Instruction Set Reference Data Contd Programming Numeric Applications Fdecstp FdivFdivp FdivrFfree ST1 Fiadd DISTANCE..TRAVELLED Fiadd Pulsecount SIFicom TOOL.NPASSES Ficom BP+4.PARMCOUNTFidivr Frequency Fild Standoff DIFild RESPONSE.COUNT Fimul BearingFist OBS.COUNTSI Fist BP.FACTOREDPULSESFistp BX.ALPHACOUNT SI Fistp CorrectedtimeFLD Reading 81.PRE88URE FLO 8AVEREADINGFldcw Controlword FLDLG2FLOL2E FLOL2TFlopi FlozFmulp ST1,ST Fmul SpeedfactorFpatan ·14. Instruction Set Reference Data Contd FptanFrstor BP Fsave BPFST ST3 FST CorrelationFST Meanreading Fstcw SavecontrolFstp BX.ADJUSTEDRPM Fstp ST2Fstp Totaldosage Fstp Regsave SIFsubr ST,ST1 Fsubr VectorsiFsubr BX.INDEX Fsubrp ST1,STFYL2X Fxch ST2FYL2XP1 Programming Facilities High-Level Languages15. PLlM-286 Built-In Procedures ASM286 Interpretation Data TypesBIT String Shorti Nteger OFFFFFF82H HEX Must Start TR E Q Status Word Record Definition17. Addressing Mode Examples Fiaooalpha FOIVRALPHA.BETAFsub Alpha SI Filo BP.BETAIt *it Sample PL/M-286 ProgramEmulation Concurrent Processing withIntel Programming Numeric Applications ·7. Sample ASM286 ProgramSample ASM286 Program Contd Managing Concurrency Instruction SynchronizationData Synchronization Error Synchronization Synchronizing References to Shared DataMOV Fsgrt System-Level Numeric Programming Page Architecture Real-Address Mode and Protected Virtual-Address ModeProcessor Extension Data Channel Dedicated and Reserved 1/0 Locations Processor Initialization and ControlSystem Initialization Recognizing. the 80287 NPXSYSTEM-LEVEL Numeric Programming Software Routine to RecognizeConfiguring the Numerics Environment Initializing NPX Processor State Following InitializationInter Handling Numeric Processing ExceptionsSimultaneous Exception Response Precedence of NPX Exceptions Numeric Programming Examples Page Chapter Numeric Programming Examples Jump Table for Examine Routine XAMNumeric Programming Examples Conditional Branching for Fxam ContdProc MOV Byte PTR IBP-121, OH Fldenv Fnsave BP-941 FLOATING-POINT to Ascii Conversion Examples It116 Ebde DoeF \ii.t 4BB Lei Function. Partitioning Special Instructions Exception ConsiderationsDescription of Operation Scaling the Value Output Format Trigonometric Calculation ExamplesCalculating Trigonometric Functions Numeric Programming Examples207 Arg 0o,3 Coce 4676 Page Machine Instruction Encoding and Decoding Page OP-A MOD OP-S Displacement Format OP-AMOD REGMachine Instruction Encoding and Decoding Table A·2. Machine Instruction Decodin.9 GuideMachine Instruction Encoding and Decoding ModooMOD01 MOD10Table A-2. Machine Instruction Decoding Guide Contd 1REG OregFstswax XXXPage Appendix Compatibility Between NPX Page Appendix B Compatibility Between 80287 NPXNI NIT Appendixc· Page Appendix C Implementing the Ieee P754 Standard Additional Software to Meet the Standard Implementing the Ieee P754 Standard Page Glossary of 80287 and Floating-Point Terminology Page Glossary FLOATING-POINT Terminology Glossary-1Inter Glossary of 80287 and FLOATING-POINT Terminology Glossary of 80287 and FLOATING-POINT Terminology Glossary-3Glossary-4 Glossary of 80287 and FLOATING-POINT Terminology Page Index Index-2 NO-WAIT Form Index-4 Inter Inter IntJ European Sales Offices