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TASKS AND STATE TRANSITIONS

Once access to the task gate has been verified, the TSS selector from the gate is read. The RPL of the TSS selector is ignored. From this point, all the checks and actions performed for a JMP or CALL to a TSS after access has been verified are performed (see section 8.4). Figure 8-4 illustrates an example of a task switch through a task gate.

		TASK A
	I SELECTOR I----		TAS~ {	LOT DESCRIPTOR
I		TASK GATE		TSS DESCRIPTOR
I		TASK GATE
	t		l'
			l'
		LOT	L
		LOT SELECTOR	L	LOT DESCRIPTOR
				TSS DESCRIPTOR
		TSS		GOT

TASK B

ff

LOT

-

LOT SELECTOR

}~ASK _

BACK LINK

TSS

G30108

Figure 8-4. Task Switch Through a Task Gate

8-9

Image 159

Intel 80286, 80287 manual ~Ask

Contents

Page Order Number Dollars ··PRICEINCall Toll Free 800 548-4725for phone orders InfefCustomer Support 80287 Programmers Reference Manual @INTELCORPORATION Organization of this Manual PrefacePage Table of Contents Extended Instruction SET Real Address ModeChapter Memory Management and Virtual Addressing Table of Contents10-5 10-110-3 10-480286/80287 Supported Data Types Flag Word ContentsDynamic Segment Relocation and Expansion of Segment Limit Code and Data Segments Assigned to a Privilege LevelReserved Exceptions and Interrupts Inter Introduction to Page Chapter Introduction to Advanced Features Modes of OperationMemory Management Protection Mechanisms Task ManagementOrganization of this Book Support for Operating SystemsRelated Publications Inter Base Architecture Page Memory Organization and Segmentation Chapter Base Architecture8000 r Bytes and Words in Memory Ascii ·3 /80287 Supported Data Types Base ArchitectureBase Architecture General Registers RegistersMemory Segmentation and Segment Registers Index, Pointer, and Base Registers Real Address Mode Segment Selector InterpretationInlel Inter Stack Operation BP Usage as a Stack Frame Base Pointer Implied Segment Usage by Index, Pointer, and Base Registers Status and Control Registers10. Flags Register Operands Addressing ModesMemory Addressing Modes Register and Immediate ModesSegment Selection Offset Computation EASE Architecture Segment Register Selection RulesPRog~~~D INPUT/OUTPUT Memory Operand AddressingModesBX, 51 13. Complex Addressing Modes OUT AL,FEOUT FF,AL Interrupts and Exceptions Hierarchy of Instruction Sets Interrupt Vector Assignments Real Address Mode 80186~80188 Page Basic Instruction Set Page General-Purpose Data Movement Instructions Data Movement InstructionsPush Stack Manipulation InstructionsBasic Instruction SET Hm====i Flag Operation with the Basic Instruction SETStatus Flags Control FlagsPrevious Push Instructions LOW Address After Before Popa Arithmetic InstructionsBasic Instruction SET Subtraction Instructions Addition InstructionsMultiplication Instructions Division Instructions Logical InstructionsBoolean Operation Instructions Wordoprnd Shift and Rotate Instructions~-i 01, I, I aI a1,1, I, I, I a1,1,1, I aI alaiI 10 01, ,1,101, 0101,1, 01 0 10 I 1I 1I 0 1I 1 1I o I o I 1 o I 1I 1111010rrG Ll 1 1 1 l 1 Type Conversion and No-Operation Instructions Test and Compare InstructionsControl Transfer Instructions Unconditional Transfer Instructions Call Instruction Conditional Transfer Instructions JLE/JNG JG/JNLEJGE/JNL JL/JNGESoftware-Generated Interrupts Character Translation and String Instructions Translate InstructionString Manipulation Instructions and Repeat Prefixes String Movement Instructions Address Manipulation Instructions Flag Control Instructions IntelFlag Transfer Instructions Packed BCD Adjustment Instructions Unpacked BCD Adjustment InstructionsBINARY-CODED Decimal Arithmetic Instructions Trusted Instructions Trusted and Privileged Restrictions on Popf and IretMachine State Instructions Processor Extension Instructions Input and Output InstructionsNumeric Data Processor Instructions Processor Extension Synchronization InstructionsBasic Instruction SET Data Transfer Instructions Page Extended Instruction Set Page Block 1/0 Instructions Chapter Extended Instruction SETHIGH-LEVEL Instructions Formal Definition of the Enter Instruction Extended Instruction SET Variable Access in Nested Procedures2b. Stack Frame for Procedure a 2d. Stack Frame for Procedure C at Level 3 Called from B Extended Instruction SET Page Real Address Mode Page Addressing and Segmentation Chapter Real Address ModeReal Address Mode Overlapping Segments to Save Physical Memory Real Address ModeInterrupt Priorities NMIIntr Reserved and Dedicated Interrupt Vectors Interrupt ProceduresESC MSW Fffoh Processor State after ResetSystem Initialization FlagsReal Address Mode ·Memory Management Virtual Addressing Page Memory Management Overview Chapter Memory Management and Virtual AddressingFormat of the Segment Selector Component Virtual AddressesAddress Spaces and Task Isolation Descriptor Tables PiDPll~1 VIRTUAL-TO-PHYSICAL Address Translation PIDPLI~1LOT Descriptor Segments and Segment DescriptorsVirtual-to-Physical Address Translation Segment Address Translation Registers Memory Management Registers~,m~ =--=--=1~~ System Address Registers Memory Management and Virtual Addressing Page Protection7 Page Chapter Protection Protection Implementation Addressing Segments of a Module within a Task Descriptor Cache Registers ProtectionSeparation of Address Spaces LOT and GOT Access ChecksLJol LIT Privilege Levels and Protection Example of Using Four Privilege LevelsPrivilege Usage Segment Descriptor ~~~/do I I LJ. ITI~~ DPLData Accesses Data Access Restriction by Privilege Level Code Segment AccessPointer Privilege Stamping via Arpl NTE R Control TransfersGates 10. Gate Descriptor Format Call Gates INTRA-LEVEL Transfers VIA Call Gate Call Gate ChecksSe!eC!0r j ,,It Niiii INTER-LEVEL Control Transfer VIA Call Gates Protection Stack Changes Caused by Call Gates 12. Stack Contents after an Inter-Level Call Inter-Level Return Checks Tasks and State Transitions Page Task State Segments and Descriptors IntroductionTask State Segment and TSS Registers Tasks and State TransitionsTask State Segment Descriptors I01 Task SwitchingTasks and State Transitions Checks Made during a Task Switch CALL/INT Iret Task LinkingTask Gate Descriptor Task Gates~ASK Page Interrupts and Exceptions Page Interrupt Descriptor Table Definition Interrupt Descriptor TableAn eve.! eXtern8~.~~t~~pr~~~~~1 Hardware Initiated InterruptsInterrupt Gates and Trap Gates Software Initiated InterruptsTrap/Interrupt Gate Descriptors SSFROMTSS--~.~r~------~l Trap and Interrupt Gate Checks Interrupts and ExceptionsInterrupt and Gate Interactions InferDeciding Between Task, Trap, and Interrupt Gates Scheduling ConsiderationsProtection Exceptions and Reserved Vectors Double Fault Interrupt Invalid OP-Code InterruptProcessor Extension Segment Overrun Interrupt Not Present Interrupt Invalid Task State Segment InterruptConditions That Invalidate the TSS Stack Fault InterruptAdditional Exceptions and Interrupts General Protection Fault InterruptIDT Single Step Interrupt InterruptSystem Control Initialization Page Descriptor Table Registers.· Chapter System Control and InitializationLocal and Global Descriptor Table Definition System Control and InitializationSystem Control Instructions MSW Bit Functions Machine Status WordESC WaitIfTS=1 03FFH InitializationReal Address Mode 10-8 Advanced Topics Page Virtual Memory Management Special Segment AttributesConforming Code Segments Expand-Down Segment Expand-Down Data SegmentsDynamic Segment Relocation and Expansion of Segment limit Pointer ValidationDescriptor Validation Pointer Integrity RPL and the Trojan Horse ProblemMultiprocessor Considerations NPX Context SwitchingAdvanced Topics Example of NPX Context SwitchingShutdown Page Appendix System Initialization Page Appendix a System Initialization System Initialization System .INITIALIZATION System Initialization Ax,.x Intel· Mov!w MovSiW AX,cl Page Appendix 80286 Instruction Set Page Appendix B 80286 Instruction SET Figure B-1. In Instruction Byte Format 80286 Instruction SETBX + D8 SI + Rb = Rw =REG = Mod=OO Mod=01 Mod=10 Mod=11Figure B-2 Ir Instruction Byte Format 80286 U\lSTRUCTION SETInstruction Clocks DescriptionFlags Modified Flags Undefined Protected Mode ExceptionsReal Address Mode Exceptions Error Codes#MP #UD#NM #DF#GP 13 General Protection Selector or Zero Error Code #MF 16 Math Fault No Error Code#MP 9 Math Unit Protection Fault No Error Code #NP 11 Not Present Selector Error Code #NM 7 No Math Unit Available No Error Code#TS 10 Invalid Task State Segment Selector Error Code #SS 12 Stack Fault Selector or Zero Error Code#UD 6 Undefined Opcode No Error Code Privilege Level and Task Switching onSwitchtasks 80286 Instruction SET 80286 Instruction SET AAA Ascii Adjust AL After Addition AAO AAD Ascii Adjust AX Before DivisionAAM D4 OAAAS AAS-ASCII Adjust AL After SubtractionADC/ ADD-Integer Addition ADCADD AND-Logical ARPL- Adjust RPL Field of Selector Bound rw,md noj=13 BOUND-Check Array Index Against BoundsCall Flags ModifiedFlags Undefined OperationCall to Call Gate Call FARCall Conforming Code Segment Call Nonconforming Code SegmentCall Task Gate Protected Mode Exceptions80286 Instruction SET Call Gate to More Privilege Call Gate to Same PrivilegeInterrupt l3 for a word operand at offset Offffh C8W Caw-Convert Byte into WordCLC CLC-Clear Carry FlagCLO CLD-Clear Direction Flag80286·INSTRUCTION SET Protected Mode ExceptionsReal Address Mode Exceptions Ell-Clear Interrupt FlagOpcode Instruction ClocksDescription CLTS-Clear Task Switched FlagCMC CMC-Complement Carry FlagCMP CMP-Compare Two OperandsCmpsw CMPS8CWD CWO-Convert Word to DoublewordDAA DAA-Decimal Adjust AL After AdditionDAS-Decimal Adjust AL After Subtraction Opcode Structlon Clocks Description DEC-Decrement byDIV -Unsigned Divide DIVebDIVew BP= Frameptr ENTER-Make Stack Frame for Procedure Parameters80286 Instruction SET Protected Mode Exceptions HLT-Halt IDIV-Signed Divide 21,mem=24 Signed multiply rw = EA word X imm. byte IMUL-Signed MultiplyOpcode Instruction Clocks Description Imul eb 21,mem=24 Signed multiply rw =IN-Input from Port Mem=7 Increment EA word by INCInsw INS/INSB/INSW-Input from Port to StringINS InsbINT3 INT IINTO-Call to Interrupt ProcedureInterrupt Interrupt to Inner PrivilegeInterrupt to Same Privilege Level #GP, #NP, #SS, and #TS, as indicated in the list above Interrupt Return IRET-Interrupt ReturnOpcode Instruction Clock Description IretInterrupt Return to Same Level Interrupt Return on Stack#GP, #NP, or #88, as indicated in the above listing JLE JAEJBE JGE80286 Instruction SET JMP-Jump Jump to Call Gate Jump FARJump Conforming Code Segment Jump Nonconforming Code SegmentJump Task State Segment Lahf LAHF-load Flags into AH Register02 Ir 14,mem=16 Load highrw= Access Rights byte, selector ewReal Address Mode Exception Instruction SETLOS/ LES-Load Doubleword Pointer LDSLES 80286 Instruction SET Protected Mode Exceptions Effective Address Offset LEA-loadLeave LEAVE-HighLevel Procedure ExitLlDT LGDTILIDT-Load Global/Interrupt Descriptor Table RegisterLgdt Load m into Global Descriptor Table regRegister LLDT-Load Local Descriptor Table RegisterLldt ew Load selector ew into Local Descriptor Table01 /6 LMSWew Mem=6 LMSW-Load Machine Status WordLock LOCK-AssertBUS Lock SignalLods LODS8Lodsw LOOP/LOOPcond-Loop Control with CX Counter 14,mem=16 Load rw = Segment Limit, selector ew LSL-LoadSegment Limit00 /3 LTR ew 17,mem=19 LTR-Load Task RegisterMem=5 Move EA byte into byte register Opcode Instruction Clocks DescriptionMem=3 Move byte register into EA byte Mem=3 Move word register into EA wordInterrupt 13 for a word operand at offset Offffh Movsw MOVS/MOVSB/MOVSW-Move Data from String to StringMovs MOVS8MUL-Unsigned Multiplication of AL or AX NEG-TwosComplement Negation NEG ebNEG ew NOP-No Operation Not NOT-OnesComplement NegationOR- Logical Inclusive or Output word AX to port number OX OUT OX,ALOutput byte AL to port number OX OUT OX,AXOuts OutsbOutsw POP SS POPInter Popa FlAGS UndefinedPopf POPF-Pop from Stack into the Flags RegisterPush SS PUSH-Push a Word onto the StackPush Push CSPUSHA-Push All General Registers PUSHF-Push Flags Register onto the Stack Push flag~ registerPushf ROR RCLRCR ROLInterrupt 13 for a word operand at offset Offffh REP Movs REP INSREP Insb REP Insw80286 Instruction SET RET RET -Return from ProcedureReturn to Outer Privilege Level Return to Same LevelSahf Sahf -Store AH into FlagsSAL SARSHR Interrupt 13 for a word operand at offset Offffh SBB SBB-Integer Subtraction With BorrowSCAS/SCASB/SCASW-Compare String Data 101 Sgdt /SIDT-Store Global/Interrupt Descriptor Table RegisterSLOT-Store Local Descriptor Table Register 103 Smsw -Store Machine Status Word104 STe-SetCarry FlagSTO STOSetDirection FlagSTI STI-Set Interrupt Enable FlagStosw StossSTR-Store Task Register 00 /1 STR ew Mem=3108 SUB SUB-Integer SubtractionTest TEST-Logical Compare111 VERR,VERW-Verifya Segment for Reading or Writing14,mem=16 Set ZF=1 if seg. can be read, selector ew 14,mem=16112 Wait WAIT-Wait Until Busy Pin Is Inactive HighXchg XCHG- Exchange Memory/Register with Register115 Xlat -Table Look-up TranslationXlat mb Set AL to memory byte Osbx + unsigned XlatbXOR XOR-Logical Exclusive orAppendix 8086/8088 Compatibility Considerations Page Table C-1. New 80286 Interrupts Software Compatibility ConsiderationsPushbp MOVBP,SP XCHGBP,BP Hardware Compatibility Considerations Page 80286/80386 Software Page 80286/80386 Softvvare 80286/80386 Software Compatibility Considerations Index-1 IndexIndex-2 Index-3 Index-4 LODS/LODSB/LODSW, 3-24, B-69Index-5 Index-6 Numeric Processor Extension NPX Page 80286 Microsystem AN Introduction toRelated Publications Organization of This ManualUnnormals-Descendents of Denormal Operands Chapter Overview of Numeric ProcessingChapter SYSTEM-LEVEL Numeric Programming 80287 Glossary of 80287 and FLOATING-POINT Terminology IndexStorage Allocation Directives TablesOverview of Numeric Processing Page Performance Introduction to the 80287 Numeric Processor ExtensionFxam StackO assumed Examine Overview of Numeric Processing± Vb2 4ac ApplicationsUpgradability PASCAL-286 FORTRAN-286 Programming InterfaceNumeric Data Types Hardware Interface~r=~=~ NPX Register Stack Numeric Processor Architecture80287 Register Set NPX Status WordStatus Word Control WordInfinity, positive Inter Tag Word Format Number System Computation FundamentalsNumber System Data Types and FormatsData Formats Binary Integers Rounding Control ·6. Rounding Modes Precision ControlSpecial Numeric Values Special Computational SituationsNonnormal Real Numbers Overview of Numeric Processing Denormalization ProcessUnnormals-Descendents of Denormal Operands FLD FrndintFsqrt FIST, FISTP, FbstpInfinity Fsqrt FLD, FBLD1 FILD2 FST,FSTPFbstp FIST, Fistp Fprem+co Frndint FxtractFtst ......1 ---- 15 bits-----l..~1 LargestSmallest Zero SmallestZero U U2U U Bits Normals Class NaNs16. Temporary Real Encodings Sign Biased Exponent Significand·16. Temporary Real Encodings Contd Invalid OperationZero Divisor Overview of Numeric Processing Denormalized Operand 17. Exception Conditions and Masked Responses Masked response to overflow exception earlier 17. Exception Conditions and Masked Responses Contd11. Arithmetic Example Using Infinity Software Exception Handling Programming Numeric Applications Page 80287 NPX Instruction SET Compatibility with the 8087 NPXNumeric Operands Data Transfer Instructions FAD D destination, sourceProgramming Numeric Applications Arithmetic Instructions Arithmetic Instructions Fdiv Azimuth FaddFsub FmulpFsubrp / /destination/source Fprem Condition Code Interpretation after Fprem Condition Code Interpretation after Fcom Programming Numeric Applications FabsFcom / /source Comparison InstructionsFxam FcomppSTO 1r FptanFYL2XP1 FpatanF2XM1 FYL2XConstant Instructions Processor Control Instructions Finitifninit Fstsw AX/FNSTSW AX FSAVE/FRSTOR Memory Layout Fstenvifldenv Memory Layout Ffree destination 12. Key to Operand Types Programming Numeric ApplicationsInstruction Execution Time 13. Execution Penalties Instruction Length ·14. Instruction Set Reference Data 14. Instruction Set Reference Data Contd Fdivr Programming Numeric Applications FdecstpFdiv FdivpFicom BP+4.PARMCOUNT Ffree ST1Fiadd DISTANCE..TRAVELLED Fiadd Pulsecount SI Ficom TOOL.NPASSESFimul Bearing Fidivr FrequencyFild Standoff DI Fild RESPONSE.COUNTFistp Correctedtime Fist OBS.COUNTSIFist BP.FACTOREDPULSES Fistp BX.ALPHACOUNT SIFLDLG2 FLD Reading 81.PRE88UREFLO 8AVEREADING Fldcw ControlwordFloz FLOL2EFLOL2T FlopiFmul Speedfactor Fmulp ST1,STFpatan Fsave BP ·14. Instruction Set Reference Data ContdFptan Frstor BPFstcw Savecontrol FST ST3FST Correlation FST MeanreadingFstp Regsave SI Fstp BX.ADJUSTEDRPMFstp ST2 Fstp TotaldosageFsubrp ST1,ST Fsubr ST,ST1Fsubr Vectorsi Fsubr BX.INDEXFxch ST2 FYL2XFYL2XP1 High-Level Languages Programming Facilities15. PLlM-286 Built-In Procedures Interpretation Data Types ASM286BIT String Shorti Nteger OFFFFFF82H HEX Must Start Status Word Record Definition TR E QFilo BP.BETA 17. Addressing Mode ExamplesFiaooalpha FOIVRALPHA.BETA Fsub Alpha SISample PL/M-286 Program It *itConcurrent Processing with Emulation·7. Sample ASM286 Program Intel Programming Numeric ApplicationsSample ASM286 Program Contd Instruction Synchronization Managing ConcurrencyData Synchronization Synchronizing References to Shared Data Error SynchronizationMOV Fsgrt System-Level Numeric Programming Page Real-Address Mode and Protected Virtual-Address Mode ArchitectureProcessor Extension Data Channel Recognizing. the 80287 NPX Dedicated and Reserved 1/0 LocationsProcessor Initialization and Control System InitializationSoftware Routine to Recognize SYSTEM-LEVEL Numeric ProgrammingConfiguring the Numerics Environment NPX Processor State Following Initialization InitializingHandling Numeric Processing Exceptions InterSimultaneous Exception Response Precedence of NPX Exceptions Numeric Programming Examples Page Chapter Numeric Programming Examples XAM Jump Table for Examine RoutineConditional Branching for Fxam Contd Numeric Programming ExamplesProc MOV Byte PTR IBP-121, OH Fldenv Fnsave BP-941 FLOATING-POINT to Ascii Conversion Examples It116 Ebde DoeF \ii.t 4BB Lei Function. Partitioning Exception Considerations Special InstructionsDescription of Operation Scaling the Value Trigonometric Calculation Examples Output FormatNumeric Programming Examples Calculating Trigonometric Functions207 Arg 0o,3 Coce 4676 Page Machine Instruction Encoding and Decoding Page REG OP-A MOD OP-S Displacement Format OP-AMODTable A·2. Machine Instruction Decodin.9 Guide Machine Instruction Encoding and DecodingMOD10 Machine Instruction Encoding and DecodingModoo MOD01Table A-2. Machine Instruction Decoding Guide Contd XXX 1REGOreg FstswaxPage Appendix Compatibility Between NPX Page 80287 NPX Appendix B Compatibility BetweenNI NIT Appendixc· Page Appendix C Implementing the Ieee P754 Standard Additional Software to Meet the Standard Implementing the Ieee P754 Standard Page Glossary of 80287 and Floating-Point Terminology Page Glossary-1 Glossary FLOATING-POINT TerminologyInter Glossary of 80287 and FLOATING-POINT Terminology Glossary-3 Glossary of 80287 and FLOATING-POINT TerminologyGlossary-4 Glossary of 80287 and FLOATING-POINT Terminology Page Index Index-2 NO-WAIT Form Index-4 Inter Inter IntJ European Sales Offices