Intel 80286, 80287 manual General Protection Fault Interrupt, Additional Exceptions and Interrupts

INTERRUPTS AND EXCEPTIONS

9.6.7 General Protection Fault (Interrupt 13)

If a protection violation occurs which is not covered in the preceding paragraphs, it is classed as Interrupt 13, a general protection fault. The error code is zero for limit violations, write to read-only segment violations, and accesses relative to DS or ES when they are zero or refer to a segment at a greater privilege level than CPL. Other access violations (e.g., a wrong descriptor type) push a non- zero error code that identifies the selector used on the stack. Error codes with bit 0 cleared and bits I5-2non-zero indicate a restartable condition.

Bit 1 of the error code identifies whether the selector is in the IDT or LDT/GDT. If bit 1=0 then bit 2 separates LDT from GDT. Bit 0 (EXT) indicates whether the exception was caused by the program or an event external to it (i.e., single stepping, an external interrupt, a processor extension not-present or a segment overrun). If bit 0 is set, the selector typically has nothing to do with the instruction that was interrupted. The selector refers instead to some step of servicing an interrupt that failed.

When bit 0 of the error code is set, the interrupted program can be restarted, except for processor extension segment overrun exceptions (see section 9.6.3). The exception with the bit 0 of the error code = 1 indicates some interrupt has been lost due to a fault in the descriptor pointed to by the error code.

A non~zero error code with bit 0 cleared may be an operand of the interrupted instruction, an operand from a gate referenced by the instruction, or a field from the invalid TSS;

During a task switch, when a general protection exception occurs, the ES and DS segment registers may not be usable for referencing memory (the selector vaues are loaded before the descriptors are checked). The general protection handler should not rely on being able to use the values found in ES, SS, and DS without causing another exception. This is because the task switch itself may have changed the values in the registers. The exception occurs in the new task and the return pointer points to the first instruction of the new task. Caution: the loading of the DS or ES descriptors may not have been completed. The exception 13 handler should ensure that the DS and ES descriptors have been properly loaded before the execution of the first instruction of the new task.

In Real Address Mode, Interrupt 13 will occur if software attempts to read or write a I6-bit word at segment offset OFFFFH.

9.7 ADDITIONAL EXCEPTIONS AND INTERRUPTS

Interrupts 0, 5, and I have not yet been discussed. Interrupt 0 is the divide-error exception, Interrupt 5 the bound-range exceeded exceptions, and Interrupt 1 the single step interrupt. The divide-error or bound-range exceptions make it appear as if that instruction had never executed: the registers are restored and the instruction can be restarted. The divide-error exception occurs during a DIY or an IDlY instruction when the quotient will be too large to be representable, or when the divisor is zero.

Interrupt 5 occurs when a value exceeds the limit set for it. A program can use the BOUND instruction to check a signed array index against signed limits defined in a two-word block of memory. The block can be locatcd just before the array to simplify addressing. The block's first word specifies the array's lower limit, thc second word specifies the array's upper limit, and a register specifies the array index to be tested.

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