Intel 80287, 80286 manual Code and Data Segments Assigned to a Privilege Level

	TABLE OF CONTENTS
Figure	Title		Page
7-1	Addressing Segments of a Module within a Task		7-3
7-2	Descriptor Cache Registers	'"	7-4
7-3	80286 Virtual Address Space		7-6
7-4	Local and Global Descriptor Table Definitions		7-7
7-5	Error Code Format (on the stack)		7-7
7-6	Code and Data Segments Assigned to a Privilege Level		7-9
7-7	Selector Fields		7-11
7-8	Access Byte Examples		7-12
7-9	Pointer Privilege Stamping		7-15
7-10	Gate Descriptor Format		7-17
7-11	Call Gate		7-19
7-12	Stack Contents after an Inter-Level Call		7-21
8-1	Task State Segment and TSS Registers		8-2
8-2	TSS Descriptor		8-4
8-3	Task Gate Descriptor		8-8
8-4	Task Switch Through a Task Gate		8-9
9-1	Interrupt Descriptor Table Definition		9-1
9-2	IDT Selector Error Code		9-2
9-3	Trap/Interrupt Gate Descriptors		9-4
9-4	Stack Layout after an Exception with an Error Code		9-5
10-1	Local and Global Descriptor Table Definition		10-2
10-2	Interrupt Descriptor Table Definition		10-2
10-3	Data Type for Global Descriptor Table and Interrupt Descriptor Table		10-3
11-1	Expand-Down Segment		11-2
11-2	Dynamic Segment Relocation and Expansion of Segment Limit	..........................	11-3
11-3	Example of NPX Context Switching		11-6
B-1	In Instruction Byte Format		B-2
B-2	Ir Instruction Byte Format		B-4
	Tables
Table	Title		Page
2-1	Implied Segment Usage by Index, Pointer, and Base Registers		2-14
2-2	Segment Register Selection Rules		2-19
2-3	Memory Operand Addressing Modes		2-21
2-4	80286 Interrupt Vector Assignments (Real Address Mode)		2-26
3-1	Status Flags'Functions		3-6
3-2	Control Flags'Functions		3-7
3-3	Interpretation of Conditional Transfers		3-20
5-1	Interrupt Processing Order		5-4
5-2	Dedicated and Reserved Interrupt Vectors in Real Address Mode		5-6
5-3	Processor State after RESET	:	5-7
7-1	Segment Access Rights Byte Format '"		7-11
7-2	Allowed Segment Types in Segment Registers	;	7-12
7-3	Call Gate Checks		7-18
7-4	Inter-Level Return Checks		7-22
8-1	Checks Made during a Task Switch		8-6
8-2	Effect of a Task Switch on BUSY and NT Bits and the Link Word		8-7
9-1	Trap and Interrupt Gate Checks		9-6
9-2	Interrupt and Gate Interactions		9-7

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