Intel 80286, 80287 manual Protection Exceptions and Reserved Vectors

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INTERRUPTS AND EXCEPTIONS

9.6 PROTECTION EXCEPTIONS AND RESERVED VECTORS

A protection violation will cause an exception, i.e., a non-maskable interrupt. Such a fault can be handled by the task that caused it if an interrupt or trap gate is used, or by a different task if a task gate is used (in the IDT).

Protection exceptions can be classified into program errors or implicit requests for service. The latter include stack overflow and not-present faults. Examples of program errors include attempting to write into a read-only segment, or violating segment limits.

Requests for service may use different interrupt vectors, but many diverse types of protection violation use the same general protection fault vector. Table 9-3 shows the reserved exceptions and interrupts. Interrupts 0-31 are reserved by Intel.

When simultaneous external interrupt requests occur, they are processed in the fixed order shown in table 9-4. For each interrupt serviced, the machine state is saved. The new CS:IP is loaded from the gate or TSS. If other interrupts remain enabled, they are processed before the first instruction of the current interrupt handler, i.e., the last interrupt processed is serviced first.

Table 9-3. Reserved Exceptions and Interrupts

Vector

Description

Restartable

Error Code

Number

on Stack

 

 

0

Divide Error Exception

Yes

No

1

Single Step Interrupt

Yes

No

2

NMI Interrupt

Yes

No

3

Breakpoint Interrupt

Yes

No

4

INTO Detected Overflow Exception

Yes

No

5

BOUND Range Exceeded Exception

Yes

No

6

Invalid Opcode Exception

Yes

No

7

Processor Extension Not Available Exception

Yes

No

8

Double Exception Detected

No

Yes (Always 0)

9

Processor Extension Segment Overrun Interrupt

No

No

10

Invalid Task State Segment

Yes

Yes

11

Segment Not Present

Yes

Yes

12

Stack Segment Overrun or Not Present

Yes

Yes

13

General Protection

Yes'

Yes

• Except for writes into read-only segments (see section 9.6)

 

Table 9-4. Interrupt Processing Order

Order

Interrupt

1

Instruction exception

2

Single step

3

NMI

4

Processor extension segment overrun

5

INTR

9-9

Page 171
Image 171
Intel 80286, 80287 manual Protection Exceptions and Reserved Vectors