Intel 80286, 80287 manual Interrupt Procedures, Reserved and Dedicated Interrupt Vectors

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REAL ADDRESS MODE

5.2.2 Interrupt Procedures

When an interrupt occurs in Real Address Mode, the 8086 performs the following sequence of steps. First, the FLAGS register, as well as the old values of CS and IP, are pushed onto the stack (see figure 5-4). The IF and TF flag bits are cleared. The vector number is then used to read the address of the interrupt service routine from the interrupt table. Execution begins at this address.

Thus, when control is passed to an interrupt service routine, the return linkage is placed on the stack, interrupts are disabled, and single-step trace (if in effect) is turned off. The IRET instruction at the end of the interrupt service routine will reverse these steps before transferring control to the program that was interrupted.

An interrupt service routine may affect registers other than other JP, CS, and FLAGS. It is the respon- sibility of an interrupt routine to save additional context information before proceeding so that the state of the machine can be restored upon completion of the interrupt service routine (PUSHA and paPA instructions are intended for these operations). Finally, execution of the IRET instruction pops the old IP, CS, and FLAGS from the stack and resumes the execution of the interrupted program.

5.2.3 Reserved and Dedicated Interrupt Vectors

In general, the system designer is free to use almost any interrupt vectors for any given purpose. Some of the lowest-numbered vectors, however, are reserved by Intel for dedicated functions; their use is specifically implied by certain types of exceptions. None of the first 32 vectors should be defined by the user; these vectors are either invoked by pre-defined exceptions or reserved by Intel for future expansion. Table 5-2 shows the dedicated and reserved vectors of the 80286 in Real Address Mode.

The purpose and function of the dedicated interrupt vectors may be summarized as follows (the saved value of CS:IP will include all leading prefixes):

Divide error (Interrupt 0). This exception will occur if the quotient is too large or an attempt is made to divide by zero using either the DlV or IDIV instruction. The saved CS:IP points at the first byte of the failing instruction. DX and AX are unchanged.

'r 'r

OLD FLAGS

INCREASING 1 OlDCS

ADDRESSES

OLD IP r--<SS:SP>

. ,~

G30108

Figure 5·4. Stack Structure after Interrupt (Real Address Mode)

5-5