Intel 80287, 80286 manual Proc

t,jUMERIC PROGRAMMING EXAMPLES

At the beginning of the prologue, CPU interrupts have been disabled. The prologue performs all functions that must be protected from possible interruption by higher-priority sources. Typically, this will involve saving CPU registers and transferring diagnostic information from the 80287 to memory. When the critical processing has been completed, the prologue may enable CPU interrupts to allow higher-priority interrupt handlers to preempt the exception handler.

The exception handler body examines the diagnostic information and makes a response that is neces- sarily application-dependent. This response may range from halting execution, to displaying a message, to attempting to repair the problem and proceed with normal execution.

The epilogue essentially reverses the actions of the prologue, restoring the CPU and the NPX so that normal execution can be resumed. The epilogue must not load an unmasked exception flag into the 80287 or another exception will be requested immediately.

Figure 4-3 through 4-5 show the ASM286 coding of three skeleton exception handlers. They show how prologues and epilogues can be written for various situations, but provide comments indicating only where the application-dependent exception handling body should be placed.

Figure 4-3 and 4-4 are very similar; their only substantial difference is their choice of instructions to save and restore the 80287. The tradeoff here is between the increased diagnostic information provided by FNSAVE and the faster execution of FNSTENV. For applications that are sensitive to interrupt latency or that do not need to examine register contents, FNSTENV reduces the duration of the "criti- cal region," during which the CPU will not recognize another interrupt request (unless it is a nonmask-

able interrupt). '

After the exception handler body, the epilogues prepare the CPU and the NPX to resume execution from the point of interruption (Le., the instruction following the one that generated the unmasked exception). Notice that the exception flags in the memory image that is loaded into the 80287 are cleared to zero prior to reloading (in fact, in these examples, the entire status word image is cleared).

The examples in figures 4-3 and 4-4 assume that the exception handler itself will not cause an unmasked exception. Where this is a possibility, the general approach shown in figure 4-5 can be employed. The basic technique is to save the full 80287 state and then to load a new control word in the prologue. Note that considerable care should be taken when designing an exception handler of this type to prevent the handler from being reentered endlessly.

	PROC
SAVE CPU REGISTERS, ALLOCATE STACK SPACE
FOR 80287	STATE IMAGE
PUSH	BP
MOV	BP,SP
SUB	SP,94
SAVE ~ULL 80287 STATE. WAIT FOR COMPLETION,
ENABLE CPU	INTERRUPTS
FNSAVE	[BP-941
FWAIT
STl

APPLICATION-DEPENDENT EXCEPTION HANDLING

CODE GOES HERE

Figure 4-3.Full-State Exception Handler

4-4