Intel 80286, 80287 manual Memory Management Registers, Segment Address Translation Registers

MEMORY MANAGEMENT AND VIRTUAL ADDRESSING

' ---------DESCRIPTOR PRIVILEGE LEVEL

'-----------PRESENT (I-yes)

DATA OR STACK SEGMENT

MSBLSB

ACCESSED (I-yes)

WRITEABLE (I-yes)

'-----EXPAND DOWN (I-down)

'------EXECUTABLE (O-no for data)

'-------(indicates segment descriptor)

'---------DESCRIPTOR PRIVILEGE LEVEL

' -- PRESENT (I-yes)

G30108

Figure 6-7. Segment Descriptor Access Bytes

6.6 MEMORY MANAGEMENT REGISTERS

The Protected Virtual Address Mode features of the 80286 operate at high performance due to exten- sions to the basic 8086 register set. Figure 6·8 illustrates that portion of the extended register structure that pertains to memory management. (For a complete summary of all Protected Mode registers, refer to section 10.1).

6.6.1 Segment Address Translation Registers

Figure 6-8 shows the segment registers CS,DS,ES, and SS. In contrast to their usual representation, however, these registers are now depicted as 64-bit registers, each with "visible" and "hidden" components.

The visible portions of these segment address translation registers are manipulated by programs exactly as if they were simply the 16-bit segment registers of Real Address Mode. By loading a segment selec- tor into one of these registers, the program makes the associated segment one of its four currently addressable segments.

6-9