Intel 80286, 80287 manual Tasks and State Transitions

TASKS AND STATE TRANSITIONS

No new instructions are required for a task switch operation. The standard 8086 JMP, CALL, IRET, or interrupt operations perform this function. The distinction between the standard instruction and a task switch is made either by the type of descriptor referenced (for CALL, JMP, or INT) or by the NT bit (for IRET) in flag word.

Using the CALL or INT instruction to switch tasks implies a return is expected from the calIed task. The JMP and IRET instructions imply no return is expected from the new task.

When NT= 1, the IRET instruction causes a return to the task that calIed the current one via CALL or INT instruction.

Access to TSS and task gate descriptors is restricted by the rules of privilege level. The data access rules are used, thereby alIowing task switches to be restricted to programs of sufficidnt privilege. Address space separation does not apply to TSS descriptors since they must be in the GDT. The access rules for interrupts are discussed in section 9.4.

The task switch operation consists of the folIowing eight steps:

1.Validate the requested task switch. For a task switch requested via a JMP, CALL, or an INT instruction, check that the current task is alIowed to switch to the requested task. The DPL of the gate or the TSS descriptor for the requested task must be greater than or equal to both the CPL and the RPL of the requesting task. If it is not, the General Protection fault (#13) will occur with an error code identifying the descriptor (i.e., the gate selector if the task switch is requested via a task gate, or the selector for the TSS if the task switch is requested via a TSS descriptor).

These checks are not performed if a task switch occurs due to an IRET instruction.

2.Check that the new TSS is present and that the new task is available (Le. not Busy). A Not Present exception (#11) is signaled if the new TSS descriptor is marked 'Not Present' (P = 0). The General Protection exception (#13) is raised if the new TSS is ll1arked 'Busy'.

The task switch operation actualIy begins now and a detailed verification of the new TSS is carried out. Conditions which may disqualify the new TSS are listed in table 8-1 along with the exception raised and the error code pushed on the stack for each case. These tests are performed at different points during the course of the folIowing remaining steps of the task switch operation.

3.Mark the new task to be BUSY by setting the 'BUSY' bit in the new TSS descriptor to 1.

4.Save the dynamic portion of the old TSS and load TR with the selector, base and limit for the new TSS. Set alI CPU registers to corresponding values from the new TSS except DS, ES, CS, SS, and LDT.

5.If nesting tasks, set the Nested Task (NT) flag in the new TSS to 1. Also set the Task Switched flag (TS) of the CPU flag register to 1.

6.Validate the LDT selector and the LDT descriptor of the new TSS. Load theLDT cache (LDTR) with the LDT descriptor.

7.Validate the SS, CS, DS, and ES fields of the new TSS and load these values in their respective caches (Le., SS, CS, DS, and ES registers).

8.Validate the IP field of the new TSS and then start executing the new task from CS:IP.

A more detailed explanation of steps 3-5 is given in Appendix B (80286 Instruction Set) under a pseudo procedure 'SWITCH_TASKS'. Notice how the exceptions described in table 8-1 may actualIy occur during a task switch. Similarly the exceptions that may occur during steps 1-2, and step 8 are explained in greater detail in the pseudo code description of the 286 instructions CALL, JMP, INT, and IRET in Appendix B. This information can be very helpful when debugging any protected mode code.

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