Intel 80287, 80286 manual Ni Nit

COMPATIBILITY BETWEEN THE 80287 NPX AND THE 8087

The processor control instructions for the 80287 may be coded using either a WAIT or No-WAIT form of mnemonic. The WAIT forms of these instructions cause ASM286 to precede the ESC instruction with a CPU WAIT instruction, in the identical manner as does ASM86.

10.A recommended way to detect the presence of an 80287 in an 80286 system (or an 8087 in an 8086 system) is shown below. It assumes that the sytem hardware causes the data bus to be high if no 80287 is present to drive the data lines during the FSTSW (Store 80287 Status Word) instruction.

FND_287:	F NI NIT		initialize numeric p,roce550r.
	FSTSTW	STAT	5tore 5tatu5 word into location
	MOV	AX,STAT	STAT.
	OR	AL , AL	Zero Flag reflect5 re5ult of OR.
	JZ	GOL2 8 7	Zero in AL mean5 80287 i5
			pre5ent.
No	80287 Pre5ent
	SMSW	AX
	OR	AX,0004H	5et EM bit in Machine Statu5
			W0 rd.
	LMSW	AX	to enable 50ftware emulation of
	JMP	CONTINUE	287.
80287 i5 pre5ent in 5ystem
GOT_287:	SMSW	AX
	OR	AX,0002H	5et MP bit in Machine Statu5 Word
	LMSW	AX	to permit normal 80287 operation
Continue
CONTINUE:			i and off we go

An 80286/80287 design must place a pullupresistor on one of the low eight data bus bits of the 80286 to be sure it is read as a high when no 80287 is present.

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