Intel 80286, 80287 manual ~-i

BASIC INSTRUCTION SET

SAL (Shift Arithmetic Left) shifts the destination byte or word operand left by one or by the number of bits specified in the count operand (an immediate value or the value contained in CL). The processor shifts zeros in from the right side of the operand as bits exit from the left side. See figure 3-6.

Example: SAL BL,2. Shifts the contents of BL left by 2 bits and replaces the two low-order bits with zeros.

Example: SAL BL,l. Shifts the contents of BL left by 1 bit and replaces the low-order bit with a zero. Because the processor does not have to decode the immediate count operand to obtain the shift count, this form of the instruction takes 2 clock cycles rather than the 6 clock 9ycles (5 cycles + 1 cycle for each bit shifted) required by the previous example.

SHL (Shift Logical Left) is physically the same instruction as SAL (see SAL above).

SHR (Shift Logical Right) shifts the destination byte or word operand right by one or by the number of bits specified in the count operand (an immediate value or the value contained in CL). The processor shifts zeros in from the left side of the operand as bits exit from the right side. See figure 3-7.

Example: SHR BYTEOPRND, CL. Shifts the contents of the memory byte labeled BYTEOPRND right by the number of bits specified in CL, and pads the left side of BYTEOPRND with an equal number of zeros.

SAR (Shift Arithmetic Right) shifts the destination byte or word operand to the right by one or by the number of bits specified in the count operand (an immediate value or the value contained in CL). The processor preserves the sign of the operand by shifting in zeros on the left side if the value is positive or by shifting by ones if the value is negative. See figure 3-8.

Example: SAR WORDPRND, 1. Shifts the contents of the memory byte labeled WORDPRND right by one, and replaces the high-order sign bit with a value equal to the original sign of

WORDPRND.

00		,	1	,	1 , I,		,	1 o		1 0		1 0	1	, I,		I,	1	, 1 0			o	1	'	, I SHLSAL OR
																								BEFORE
				,	I,	I,						I,		,	1 , I,						,		,	AFTER
			1				1 0	1	0	1	0		1				1	0	o	1				1 o I SALSHL BYOR
[!] O-i'																								181T
		,	1 ,		1 ,	1 ,					, I,													AFTER
0~-i							o	1	o	1			1 0		1 0	o	1 0		o	1	o	1	o 1 o I ~~t~~
																								8 BITS
OF	CF											OPERAND

Both SAL and SHL ahtft the blta In the reglater or memory operand to the lell by the specilled number 01 bit positions. CF receives the laat bit ahilled out 01 the lell 01 the operand. SAL and SHL ahlltln zeroa to 1111 the vacated bit locations. Theae Inatructlona operate on byte operand a aa well aa word operanda.

G30108

Figure 3-6.SAL and SHL

3-11