Intel 80287, 80286 manual Div,Idiv, Esc

REAL ADDRESS MODE

Table 5-2. Dedicated and Reserved Interrupt Vectors in Real Address Mode

Function	Interrupt	Related
	Number	Instructions
Divide error exception	0	DIV,IDIV
Single step interrupt	1	All
NMI interrupt	2	All
Breakpoint interrupt	3	INT
INTO detected overflow exception	4	INTO
BOUND range exceeded exception	5	BOUND
Invalid opcode exception	6	Any undefined opcode
Processor extension not available	7	ESC or WAIT
exception
Interrupt table limit too small	8	LlDT
Processor extension segment overrun	9	ESC
interrupt
Segment overrun exception	13	Any memory reference
		instruction that attempts

to reference 16-bit word at offset OFFFFH.

Return Address

Before Instruction

Causing Exception?

Yes

N/A

N/A

N/A

No

Yes

Yes

Yes

Yes

Yes

Yes

Reserved	10-12,14,15
Processor extension error interrupt	16	ESC or WAIT	N/A
Reserved	17-31
IUser defined	132-255

N/A = Not Applicable

Single-Step (Interrupt 1). This interrupt will occur after each instruction if the Trap Flag (TF) bit of the FLAGS register is set. Of course, TF is cleared upon entry to this or any other interrupt to prevent infinite recursion. The saved value of CS:IP will point to the next instruction.

Nonmaskable (Interrupt 2). This interrupt will occur upon receipt of an external signal on the NMI pin. Typically, the nonmaskable interrupt is used to implement power-failJauto-restart procedures. The saved value of CS:IP will.point to the first byte of the interrupted instruction.

Breakpoint (Interrupt 3). Execution of the one-byte breakpoint instruction causes this interrupt to occur. This instruction is useful for the implementation of software debuggers since it requires only one code byte and can be substituted for any instruction opcode byte. The saved value of CS:IP will point to the next instruction.

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