Intel 80286, 80287 manual Interrupt Descriptor Table Definition

CHAPTER 9

INTERRUPTS AND EXCEPTIONS

Interrupts and exceptions are special cases of control transfer within a program. An interrupt occurs as a result of an event that is independent of the currently executing program, while exceptions are a direct result of the program currently being executed, Interrupts may be external or internal. External interrupts are generated by either the INTR or NMI input pins. Internal interrupts are caused by the INT instruction. Exceptions occur when an instruction cannot be completed normally. Although their causes differ, interrupts and exceptions use the same control transfer techniques and privilege rules; therefore, in the following discussions the term interrupt will also apply to exceptions.

The program used to service an interrupt may execute in the context of .the task that caused the interrupt (i.e., used the same TSS, LDT, stacks, etc.) or may be a separate task. The choice depends on the function to be performed and the level of isolation required.

9.1 INTERRUPT DESCRIPTOR TABLE

Many different events may cause an interrupt. To allow the reason for an interrupt to be easily identi- fied, each interrupt source is given a number called the interrupt vector. Up to 256 different interrupt vectors (numbers) are possible. See figure 9-1.

A table is used to define the handler for each interrupt vector. The Interrupt Descriptor Table (IDT) defines the interrupt handlers for up to 256 different interrupts. The IDT is in physical memory, pointed to by the contents of the on-chip IDT register that contains a 24-bit base and a 16-bit limit. The IDTR is normally loaded with the LIDT instruction by code that executes at privilege level 0 during system initialization. The IDT may be located anywhere in the physical address space of the 80286.

			MEMORY	,
			'I'	THE lOT MAY
			GATE FOR	CONTAIN
				INTERRUPT
			INTERRUPT #n
				GATES, TRAPS
			GATE FOR	OR TASK GATES
				ONLY.
			INTERRUPT #n-1
			·	INTERRUPT
	cPU	r+-		DESCRIPTOR
				TABLE
			·	(lOT)
	15	0	·
	JlOT LIMIT		GATE FOR
		1-1-	INTERRUPT # 1
			GATE FOR
IOTR	l lOT BASE		INTERRUPT #0
	23	0	,>,	"

G30108

Figure 9-1. Interrupt Descriptor Table Definition

9-1