Intel 80287, 80286 manual Software Exception Handling

OVERVIEW OF NUMERIC PROCESSING

Software Exception Handling

If the NPX encounters an unmasked exception condition, it signals the exception to the 80286 CPU using the ERROR status line between the two processors.

The next time the 80286 CPU encounters aWAIT or ESC instruction in its instruction stream, the 80286 will detect the active condition of the ERROR status line and automatically trap to an exception response routine using interrupt #16-the Processor Extension Error exception.

This exception response routine is typically a part of the systems software. Typical exception responses may include:

•Incrementing an exception counter for later display or printing

•Printing or displaying diagnostic information (e.g., the 80287 environment and registers)

•Aborting further execution

Using the exception pointers to build an instruction that will run without exception and executing it

Application programmers on 80286 systems having systems software support for the 80287 NPX should consult their references for the appropriate system response to NPX exceptions. For systems program- mers, specific details on writing software exception handlers are included in the section "System-Level Numeric Programming" later in this manual.

The 80287 NPX differs from the 8087 NPX in the manner in which numeric exceptions are signalled to the CPU; the 8087 requires an interrupt controller (8259A) to interrupt the CPU, while the 80287 does not. Programmers upgrading 8087 software to operate on an 80287 should be aware of these differences and any implications they might have on numeric exception-handling software. Appendix B explains the differences between the 80287 and the 8087 NPX in greater detail.

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