Intel 80287, 80286 manual #GP, #NP, #SS, and #TS, as indicated in the list above

THE 80286 INSTRUCTION SET

Index must be within GOT limits else #GP (TSS selector)

AR byte must specify available TSS (bottom bits 00001) else #GP (TSS selector) Task State Segment must be PRESENT else #NP (TSS selector)

SWITCH3ASKS with nesting to TSS

If interrupt was caused by fault with error code then

Stack limits must allow push of two more bytes else #SS(O) Push error code onto stack

IP must be in CS limit else #GP(O)

NOTE

EXT is 1 if an external event (Le., a single step, an external interrupt, an MF exception, or an MP exception) caused the interrupt; 0 if not (Le., an INT instruction or other exceptions).

PROTECTED MODE EXCEPTIONS

#GP, #NP, #SS, and #TS, as indicated in the list above.

REAL ADDRESS MODE EXCEPTIONS

None; the 80286 will shut down if the SP = 1, 3, or 5 before executing the INT or INTO instruction- due to lack of stack space.

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