Tasks and State Transitions | Intel 80287, 80286 specification

TASKS AND STATE TRANSITIONS

		CPU	,			INTEL RESERVED
			,			plop+1 TYPE I 8A5E 23. 16
	TASK REGISTER			T55		plop+1 TYPE I 8A5E 23. 16
	0----... DESCRIPTOR					8A5E,5_0
r---------,
	IS	0
I	PROGRAM INVISIBLE		I			LIMIT,S·O
I	15	0	I			LIMIT,S·O
I	15	0	I
I	I	LIMIT	]i	------		------------
I	I	LIMIT
: I	BASE
: I	BASE				,		,
I		0	I		,		,
L ____ ---			_...J			IS	0

TASK LOT SELECTOR

TYPE DESCRIPTION

1AN AVAILABLE TASK STATE SEGMENT MAY BE USED AS THE DESTINATION OF A TASK SWITCH OPERATION.

A BUSY TASK STATE SEGMENT CANNOT BE USED AS THE DESTINATION OF A TASK SWITCH.

BYTE

OFFSET

/(1)

42 --------

OS SELECTOR

55 SelECTOR

CS SELECTOR

ES SELECTOR

01

51

BP

SP

BX

TASK OX

STATE

SEGMENT ex

AX

FLAG WORD

IP {ENTRY POINT)

40P

1

38

0

36

34

32

30

28CURRENT TASK

26 STATE

24

22

20

18

16

14

DESCRIPTION

BASE AND LIMIT FIEL.DS ARE VALID

SEGMENT IS NOT PRESENT IN MEMORY. BASE AND LIMIT ARE NOT DEFINED

(2)

55 FOA CPL 2

SP FOR CPL 2

55 FOR CPL 1

SP FOR CPt: 1

58 FOR CPL 0

5P FDA CPl 0

BACK LINK SELECTOR TO TSS

(1)NEVER ALTERED (STATIC) AFTER INITIALIZATION BY 0.5.

"!"~!: VAIJ)I=c:..4.~ INITIAliZED FOR THIS TASK ARE ALWAYS VALID SS:SP VALUES TO USE UPON ENTRY TO THAT PRIVILEGE LEVEL (0, 1, OR 2) FROM A LEVEL OF LESSER PRIVILEGE.

(2)CHANGED DURING TASK SWITCH

12)

10

BJ STACKSINITIAL (1)

:FOR CPL 0.1.2

0 _

G3010B

Figure 8-1. Task State Segment and TSS Registers

8-2

Image 152

Intel 80287, 80286 manual Tasks and State Transitions, Task State Segment and TSS Registers

Contents

Page ··PRICEIN Order Number Dollars Infef Call Toll Free 800 548-4725for phone orders Customer Support 80287 Programmers Reference Manual @INTELCORPORATION Preface Organization of this ManualPage Table of Contents Real Address Mode Extended Instruction SET Table of Contents Chapter Memory Management and Virtual Addressing 10-1 10-310-4 10-5 Flag Word Contents 80286/80287 Supported Data Types Code and Data Segments Assigned to a Privilege Level Dynamic Segment Relocation and Expansion of Segment Limit Reserved Exceptions and Interrupts Inter Introduction to Page Chapter Introduction to Memory Management Advanced FeaturesModes of Operation Task Management Protection Mechanisms Support for Operating Systems Organization of this Book Related Publications Inter Base Architecture Page Chapter Base Architecture Memory Organization and Segmentation 8000 r Bytes and Words in Memory Ascii Base Architecture ·3 /80287 Supported Data Types Base Architecture Registers General Registers Memory Segmentation and Segment Registers Real Address Mode Segment Selector Interpretation Index, Pointer, and Base Registers Inlel Inter Stack Operation BP Usage as a Stack Frame Base Pointer Status and Control Registers Implied Segment Usage by Index, Pointer, and Base Registers 10. Flags Register Addressing Modes Operands Register and Immediate Modes Memory Addressing Modes Segment Selection EASE Architecture Segment Register Selection Rules Offset Computation PRog~~~D BX, 51 INPUT/OUTPUTMemory Operand AddressingModes 13. Complex Addressing Modes OUT FF,AL OUTAL,FE Interrupts and Exceptions Hierarchy of Instruction Sets Interrupt Vector Assignments Real Address Mode 80186~80188 Page Basic Instruction Set Page Data Movement Instructions General-Purpose Data Movement Instructions Stack Manipulation Instructions Push Basic Instruction SET Flag Operation with the Basic Instruction SET Status FlagsControl Flags Hm====i Arithmetic Instructions Previous Push Instructions LOW Address After Before Popa Basic Instruction SET Addition Instructions Subtraction Instructions Multiplication Instructions Boolean Operation Instructions Division InstructionsLogical Instructions Shift and Rotate Instructions Wordoprnd ~-i 01, I, I aI a1,1, I, I, I a1,1,1, I aI alaiI 10 01, ,1,101, 0101,1, 01 0 10 I 1I 1I 0 1I 1 1I o I o I 1 o I 1I 1111010rrG Ll 1 1 1 l 1 Control Transfer Instructions Type Conversion and No-Operation InstructionsTest and Compare Instructions Unconditional Transfer Instructions Call Instruction Conditional Transfer Instructions JG/JNLE JGE/JNLJL/JNGE JLE/JNG Software-Generated Interrupts String Manipulation Instructions and Repeat Prefixes Character Translation and String InstructionsTranslate Instruction String Movement Instructions Address Manipulation Instructions Intel Flag Control Instructions Flag Transfer Instructions BINARY-CODED Decimal Arithmetic Instructions Packed BCD Adjustment InstructionsUnpacked BCD Adjustment Instructions Machine State Instructions Trusted InstructionsTrusted and Privileged Restrictions on Popf and Iret Input and Output Instructions Processor Extension Instructions Processor Extension Synchronization Instructions Numeric Data Processor Instructions Basic Instruction SET Data Transfer Instructions Page Extended Instruction Set Page Chapter Extended Instruction SET Block 1/0 Instructions HIGH-LEVEL Instructions Formal Definition of the Enter Instruction Variable Access in Nested Procedures Extended Instruction SET 2b. Stack Frame for Procedure a 2d. Stack Frame for Procedure C at Level 3 Called from B Extended Instruction SET Page Real Address Mode Page Chapter Real Address Mode Addressing and Segmentation Real Address Mode Real Address Mode Overlapping Segments to Save Physical Memory Intr Interrupt PrioritiesNMI Interrupt Procedures Reserved and Dedicated Interrupt Vectors ESC Processor State after Reset System InitializationFlags MSW Fffoh Real Address Mode ·Memory Management Virtual Addressing Page Chapter Memory Management and Virtual Addressing Memory Management Overview Virtual Addresses Format of the Segment Selector Component Address Spaces and Task Isolation Descriptor Tables PiDPll~1 PIDPLI~1 VIRTUAL-TO-PHYSICAL Address Translation Segments and Segment Descriptors LOT Descriptor Virtual-to-Physical Address Translation Memory Management Registers Segment Address Translation Registers ~,m~ =--=--=1~~ System Address Registers Memory Management and Virtual Addressing Page Protection7 Page Chapter Protection Protection Implementation Addressing Segments of a Module within a Task Protection Descriptor Cache Registers LOT and GOT Access Checks Separation of Address Spaces LJol LIT Example of Using Four Privilege Levels Privilege Levels and Protection Privilege Usage Segment Descriptor DPL ~~~/do I I LJ. ITI~~ Data Accesses Code Segment Access Data Access Restriction by Privilege Level Pointer Privilege Stamping via Arpl Control Transfers NTE R Gates 10. Gate Descriptor Format Call Gates Se!eC!0r j ,,It Niiii INTRA-LEVEL Transfers VIA Call GateCall Gate Checks INTER-LEVEL Control Transfer VIA Call Gates Protection Stack Changes Caused by Call Gates 12. Stack Contents after an Inter-Level Call Inter-Level Return Checks Tasks and State Transitions Page Introduction Task State Segments and Descriptors Tasks and State Transitions Task State Segment and TSS Registers Task State Segment Descriptors Task Switching I01 Tasks and State Transitions Checks Made during a Task Switch Task Linking CALL/INT Iret Task Gates Task Gate Descriptor ~ASK Page Interrupts and Exceptions Page Interrupt Descriptor Table Interrupt Descriptor Table Definition Hardware Initiated Interrupts An eve.! eXtern8~.~~t~~pr~~~~~1 Software Initiated Interrupts Interrupt Gates and Trap Gates Trap/Interrupt Gate Descriptors SSFROMTSS--~.~r~------~l Interrupts and Exceptions Trap and Interrupt Gate Checks Infer Interrupt and Gate Interactions Scheduling Considerations Deciding Between Task, Trap, and Interrupt Gates Protection Exceptions and Reserved Vectors Processor Extension Segment Overrun Interrupt Double Fault InterruptInvalid OP-Code Interrupt Invalid Task State Segment Interrupt Not Present Interrupt Stack Fault Interrupt Conditions That Invalidate the TSS General Protection Fault Interrupt Additional Exceptions and Interrupts Single Step Interrupt Interrupt IDT System Control Initialization Page Chapter System Control and Initialization Descriptor Table Registers.· System Control and Initialization Local and Global Descriptor Table Definition System Control Instructions Machine Status Word MSW Bit Functions IfTS=1 ESCWait Initialization 03FFH Real Address Mode 10-8 Advanced Topics Page Conforming Code Segments Virtual Memory ManagementSpecial Segment Attributes Expand-Down Data Segments Expand-Down Segment Pointer Validation Dynamic Segment Relocation and Expansion of Segment limit Pointer Integrity RPL and the Trojan Horse Problem Descriptor Validation NPX Context Switching Multiprocessor Considerations Example of NPX Context Switching Advanced Topics Shutdown Page Appendix System Initialization Page Appendix a System Initialization System Initialization System .INITIALIZATION System Initialization Ax,.x Intel· Mov!w MovSiW AX,cl Page Appendix 80286 Instruction Set Page Appendix B 80286 Instruction SET 80286 Instruction SET Figure B-1. In Instruction Byte Format Rb = Rw = REG =Mod=OO Mod=01 Mod=10 Mod=11 BX + D8 SI + 80286 U\lSTRUCTION SET Figure B-2 Ir Instruction Byte Format Instruction Flags Modified ClocksDescription Protected Mode Exceptions Real Address Mode ExceptionsError Codes Flags Undefined #UD #NM#DF #MP #MP 9 Math Unit Protection Fault No Error Code #GP 13 General Protection Selector or Zero Error Code#MF 16 Math Fault No Error Code #NM 7 No Math Unit Available No Error Code #NP 11 Not Present Selector Error Code #SS 12 Stack Fault Selector or Zero Error Code #TS 10 Invalid Task State Segment Selector Error Code Switchtasks #UD 6 Undefined Opcode No Error CodePrivilege Level and Task Switching on 80286 Instruction SET 80286 Instruction SET AAA Ascii Adjust AL After Addition AAD Ascii Adjust AX Before Division AAO D4 OA AAM AAS-ASCII Adjust AL After Subtraction AAS ADD ADC/ ADD-Integer AdditionADC AND-Logical ARPL- Adjust RPL Field of Selector BOUND-Check Array Index Against Bounds Bound rw,md noj=13 Flags Modified Flags UndefinedOperation Call Call FAR Call Conforming Code SegmentCall Nonconforming Code Segment Call to Call Gate Protected Mode Exceptions 80286 Instruction SET Call Gate to More PrivilegeCall Gate to Same Privilege Call Task Gate Interrupt l3 for a word operand at offset Offffh Caw-Convert Byte into Word C8W CLC-Clear Carry Flag CLC CLD-Clear Direction Flag CLO Protected Mode Exceptions Real Address Mode ExceptionsEll-Clear Interrupt Flag 80286·INSTRUCTION SET CLTS-Clear Task Switched Flag Opcode Instruction ClocksDescription CMC-Complement Carry Flag CMC CMP-Compare Two Operands CMP CMPS8 Cmpsw CWO-Convert Word to Doubleword CWD DAA-Decimal Adjust AL After Addition DAA DAS-Decimal Adjust AL After Subtraction DEC-Decrement by Opcode Structlon Clocks Description DIVew DIV -Unsigned DivideDIVeb ENTER-Make Stack Frame for Procedure Parameters BP= Frameptr 80286 Instruction SET Protected Mode Exceptions HLT-Halt IDIV-Signed Divide IMUL-Signed Multiply Opcode Instruction Clocks Description Imul eb21,mem=24 Signed multiply rw = 21,mem=24 Signed multiply rw = EA word X imm. byte IN-Input from Port INC Mem=7 Increment EA word by INS/INSB/INSW-Input from Port to String INSInsb Insw INT IINTO-Call to Interrupt Procedure INT3 Interrupt to Same Privilege Level InterruptInterrupt to Inner Privilege #GP, #NP, #SS, and #TS, as indicated in the list above IRET-Interrupt Return Opcode Instruction Clock DescriptionIret Interrupt Return Interrupt Return on Stack Interrupt Return to Same Level #GP, #NP, or #88, as indicated in the above listing JAE JBEJGE JLE 80286 Instruction SET JMP-Jump Jump FAR Jump Conforming Code SegmentJump Nonconforming Code Segment Jump to Call Gate Jump Task State Segment LAHF-load Flags into AH Register Lahf 14,mem=16 Load highrw= Access Rights byte, selector ew Real Address Mode ExceptionInstruction SET 02 Ir LES LOS/ LES-Load Doubleword PointerLDS 80286 Instruction SET Protected Mode Exceptions LEA-load Effective Address Offset LEAVE-HighLevel Procedure Exit Leave LGDTILIDT-Load Global/Interrupt Descriptor Table Register LgdtLoad m into Global Descriptor Table reg LlDT LLDT-Load Local Descriptor Table Register Lldt ewLoad selector ew into Local Descriptor Table Register LMSW-Load Machine Status Word 01 /6 LMSWew Mem=6 LOCK-AssertBUS Lock Signal Lock Lodsw LodsLODS8 LOOP/LOOPcond-Loop Control with CX Counter LSL-LoadSegment Limit 14,mem=16 Load rw = Segment Limit, selector ew LTR-Load Task Register 00 /3 LTR ew 17,mem=19 Opcode Instruction Clocks Description Mem=3 Move byte register into EA byteMem=3 Move word register into EA word Mem=5 Move EA byte into byte register Interrupt 13 for a word operand at offset Offffh MOVS/MOVSB/MOVSW-Move Data from String to String MovsMOVS8 Movsw MUL-Unsigned Multiplication of AL or AX NEG ew NEG-TwosComplement NegationNEG eb NOP-No Operation NOT-OnesComplement Negation Not OR- Logical Inclusive or OUT OX,AL Output byte AL to port number OXOUT OX,AX Output word AX to port number OX Outsw OutsOutsb POP POP SS Inter FlAGS Undefined Popa POPF-Pop from Stack into the Flags Register Popf PUSH-Push a Word onto the Stack PushPush CS Push SS PUSHA-Push All General Registers Pushf PUSHF-Push Flags Register onto the StackPush flag~ register RCL RCRROL ROR Interrupt 13 for a word operand at offset Offffh REP INS REP InsbREP Insw REP Movs 80286 Instruction SET RET -Return from Procedure RET Return to Same Level Return to Outer Privilege Level Sahf -Store AH into Flags Sahf SHR SALSAR Interrupt 13 for a word operand at offset Offffh SBB-Integer Subtraction With Borrow SBB SCAS/SCASB/SCASW-Compare String Data Sgdt /SIDT-Store Global/Interrupt Descriptor Table Register 101 SLOT-Store Local Descriptor Table Register Smsw -Store Machine Status Word 103 STe-SetCarry Flag 104 STOSetDirection Flag STO STI-Set Interrupt Enable Flag STI Stoss Stosw 108 STR-Store Task Register00 /1 STR ew Mem=3 SUB-Integer Subtraction SUB TEST-Logical Compare Test VERR,VERW-Verifya Segment for Reading or Writing 14,mem=16 Set ZF=1 if seg. can be read, selector ew14,mem=16 111 112 WAIT-Wait Until Busy Pin Is Inactive High Wait XCHG- Exchange Memory/Register with Register Xchg Xlat -Table Look-up Translation Xlat mb Set AL to memory byte Osbx + unsignedXlatb 115 XOR-Logical Exclusive or XOR Appendix 8086/8088 Compatibility Considerations Page Software Compatibility Considerations Table C-1. New 80286 Interrupts Pushbp MOVBP,SP XCHGBP,BP Hardware Compatibility Considerations Page 80286/80386 Software Page 80286/80386 Softvvare 80286/80386 Software Compatibility Considerations Index Index-1 Index-2 Index-3 LODS/LODSB/LODSW, 3-24, B-69 Index-4 Index-5 Index-6 Numeric Processor Extension NPX Page AN Introduction to 80286 Microsystem Organization of This Manual Related Publications Chapter Overview of Numeric Processing Unnormals-Descendents of Denormal Operands Chapter SYSTEM-LEVEL Numeric Programming Glossary of 80287 and FLOATING-POINT Terminology Index 80287 Tables Storage Allocation Directives Overview of Numeric Processing Page Introduction to the 80287 Numeric Processor Extension Performance Overview of Numeric Processing Fxam StackO assumed Examine Applications ± Vb2 4ac Upgradability Programming Interface PASCAL-286 FORTRAN-286 Hardware Interface Numeric Data Types ~r=~=~ Numeric Processor Architecture NPX Register Stack NPX Status Word 80287 Register Set Control Word Status Word Infinity, positive Inter Tag Word Format Computation Fundamentals Number System Data Types and Formats Number System Data Formats Binary Integers Rounding Control Precision Control ·6. Rounding Modes Special Computational Situations Special Numeric Values Nonnormal Real Numbers Denormalization Process Overview of Numeric Processing Unnormals-Descendents of Denormal Operands Frndint FsqrtFIST, FISTP, Fbstp FLD Infinity FLD, FBLD1 FILD2 FST,FSTP Fbstp FIST, FistpFprem Fsqrt +co Ftst FrndintFxtract Largest SmallestZero Smallest ......1 ---- 15 bits-----l..~1 U U ZeroU U2 Bits Class NaNs 16. Temporary Real Encodings Sign Biased ExponentSignificand· Normals Zero Divisor 16. Temporary Real Encodings ContdInvalid Operation Overview of Numeric Processing Denormalized Operand 17. Exception Conditions and Masked Responses 17. Exception Conditions and Masked Responses Contd Masked response to overflow exception earlier 11. Arithmetic Example Using Infinity Software Exception Handling Programming Numeric Applications Page Numeric Operands 80287 NPX Instruction SETCompatibility with the 8087 NPX FAD D destination, source Data Transfer Instructions Programming Numeric Applications Arithmetic Instructions Arithmetic Instructions Fadd FsubFmulp Fdiv Azimuth Fsubrp / /destination/source Fprem Condition Code Interpretation after Fprem Programming Numeric Applications Fabs Fcom / /sourceComparison Instructions Condition Code Interpretation after Fcom Fcompp Fxam Fptan STO 1r Fpatan F2XM1FYL2X FYL2XP1 Constant Instructions Processor Control Instructions Finitifninit Fstsw AX/FNSTSW AX FSAVE/FRSTOR Memory Layout Fstenvifldenv Memory Layout Ffree destination Instruction Execution Time 12. Key to Operand TypesProgramming Numeric Applications 13. Execution Penalties Instruction Length ·14. Instruction Set Reference Data 14. Instruction Set Reference Data Contd Programming Numeric Applications Fdecstp FdivFdivp Fdivr Ffree ST1 Fiadd DISTANCE..TRAVELLED Fiadd Pulsecount SIFicom TOOL.NPASSES Ficom BP+4.PARMCOUNT Fidivr Frequency Fild Standoff DIFild RESPONSE.COUNT Fimul Bearing Fist OBS.COUNTSI Fist BP.FACTOREDPULSESFistp BX.ALPHACOUNT SI Fistp Correctedtime FLD Reading 81.PRE88URE FLO 8AVEREADINGFldcw Controlword FLDLG2 FLOL2E FLOL2TFlopi Floz Fpatan Fmul SpeedfactorFmulp ST1,ST ·14. Instruction Set Reference Data Contd FptanFrstor BP Fsave BP FST ST3 FST CorrelationFST Meanreading Fstcw Savecontrol Fstp BX.ADJUSTEDRPM Fstp ST2Fstp Totaldosage Fstp Regsave SI Fsubr ST,ST1 Fsubr VectorsiFsubr BX.INDEX Fsubrp ST1,ST FYL2XP1 Fxch ST2FYL2X Programming Facilities High-Level Languages 15. PLlM-286 Built-In Procedures ASM286 Interpretation Data Types BIT String Shorti Nteger OFFFFFF82H HEX Must Start TR E Q Status Word Record Definition 17. Addressing Mode Examples Fiaooalpha FOIVRALPHA.BETAFsub Alpha SI Filo BP.BETA It *it Sample PL/M-286 Program Emulation Concurrent Processing with Intel Programming Numeric Applications ·7. Sample ASM286 Program Sample ASM286 Program Contd Managing Concurrency Instruction Synchronization Data Synchronization Error Synchronization Synchronizing References to Shared Data MOV Fsgrt System-Level Numeric Programming Page Processor Extension Data Channel Real-Address Mode and Protected Virtual-Address ModeArchitecture Dedicated and Reserved 1/0 Locations Processor Initialization and ControlSystem Initialization Recognizing. the 80287 NPX SYSTEM-LEVEL Numeric Programming Software Routine to Recognize Configuring the Numerics Environment Initializing NPX Processor State Following Initialization Inter Handling Numeric Processing Exceptions Simultaneous Exception Response Precedence of NPX Exceptions Numeric Programming Examples Page Chapter Numeric Programming Examples Jump Table for Examine Routine XAM Numeric Programming Examples Conditional Branching for Fxam Contd Proc MOV Byte PTR IBP-121, OH Fldenv Fnsave BP-941 FLOATING-POINT to Ascii Conversion Examples It116 Ebde DoeF \ii.t 4BB Lei Function. Partitioning Description of Operation Exception ConsiderationsSpecial Instructions Scaling the Value Output Format Trigonometric Calculation Examples Calculating Trigonometric Functions Numeric Programming Examples 207 Arg 0o,3 Coce 4676 Page Machine Instruction Encoding and Decoding Page OP-A MOD OP-S Displacement Format OP-AMOD REG Machine Instruction Encoding and Decoding Table A·2. Machine Instruction Decodin.9 Guide Machine Instruction Encoding and Decoding ModooMOD01 MOD10 Table A-2. Machine Instruction Decoding Guide Contd 1REG OregFstswax XXXPage Appendix Compatibility Between NPX Page Appendix B Compatibility Between 80287 NPX NI NIT Appendixc· Page Appendix C Implementing the Ieee P754 Standard Additional Software to Meet the Standard Implementing the Ieee P754 Standard Page Glossary of 80287 and Floating-Point Terminology Page Glossary FLOATING-POINT Terminology Glossary-1 Inter Glossary of 80287 and FLOATING-POINT Terminology Glossary of 80287 and FLOATING-POINT Terminology Glossary-3 Glossary-4 Glossary of 80287 and FLOATING-POINT Terminology Page Index Index-2 NO-WAIT Form Index-4 Inter Inter IntJ European Sales Offices