Intel 80287, 80286 #UD 6 Undefined Opcode No Error Code, Privilege Level and Task Switching on

THE 80286 INSTRUCTION SET

#UD 6 Undefined Opcode (No Error Code)

This exception is generated when an invalid operation code is detected in the instruction stream. Following are the cases in which #UD can occur:

1.The first byte of an instruction is completely invalid (e.g., 64H).

2.The first byte indicates a 2-byte opcode and the second byte is invalid (e.g., OFH followed by OFFH).

3.An invalid register is used with an otherwise valid opcode (e.g., MOV CS,AX).

4.An invalid opcode extension is given in the REG field of the ModRM byte (e.g., OF6H /1).

5.A register operand is given in an instruction that requires a memory operand (e.g., LGDT AX).

Since the offending opcode will always be invalid, it cannot be restarted. However, the #UD handler might be coded to implement an extension of the 80286 instruction set. In that case, the handler could advance the return pointer beyond the extended instruction and return control to the program after the extended instruction is emulated. Any such extensions may be incompatible with the 80386.

Privilege Level and Task Switching on the 80286

The 80286 supports many of the functions necessary to implement a protected, multi-tasking operating system in hardware. This support is provided not by additional instructions, but by extension of the semantics of 8086/8088 instructions that change the value of CS:IP.

Whenever the 80286 performs an inter-segment jump, call, interrupt, or return, it consults the Access Rights (AR) byte found in the descriptor table entry of the selector associated with the new CS value. The AR byte determines whether the long jump being made is through a gate, or is a task switch, or is a simple long jump to the same privilege level. Table B-3 lists the possible values of the AR byte. The "privilege" headings at the top of the table give the Descriptor Privilege Level, which is referred to as the DPL within the instruction descriptions.

Each of the CALL, INT, IRET, JMP, and RET instructions contains on its instruction set pages a listing of the access rights checking and actions taken to implement the instruction. Instructions involv- ing task switches contain the symbol SWITCH_TASKS, which is an abbreviation for the following list of checks and actions:

SWITCH_TASKS:

Locked set AR byte of new TSS descriptor to Busy TSS (Bit 1 = 1)

Current TSS cache must be valid with limit;::: 41 else #TS (error code will be new TSS, but back link points at old TSS)

Save machine state in current TSS

If nesting tasks, set the new TSS link to the current TSS selector

Any exception will be in new context Else set the AR byte of current TSS descriptor to Available TSS (Bit 1 = 0)

Set the current TR to selector, base, and limit of new 188 New TSS limit;::: 43 else #TS (new TSS)

Set all machine registers to values from newTSS without loading descriptors for OS, ES, CS, SS, LOT Clear valid flags for LOT,SS,CS,OS,ES (not valid yet)

If nesting tasks, set the Nested Task flag to 1 Set the Task Switched flag to 1

LOT from the new TSS must be within GOT table limits else #TS(LOT) AR byte from LOT descriptor must specify LOT segment else #TS(LOT) AR byte from LOT descriptor must indicate PRESENT else #TS(LOT) Load LOT cache with new LOT descriptor and set valid bit

B-12