Intel 80286, 80287 manual Sal, Sar, Shr

THE 80286 INSTRUCTION SET

SAL/SARISHL/SHR-Shift Instructions

Opcode			Instruction		Clocks-N'	Description
DO	/4		SAL	eb,1	2,mem=7	Multiply EA byte by 2, once
02	/4		SAL	eb,CL	5,mem=8	Multiply EA byte by 2, CL times
CO	/4	db	SAL	eb,db	5,mem=8	Multiply EA byte by 2, db times
01	/4		SAL	ew,1	2,mem=7	Multiply EA word by 2, once
03	/4		SAL	ew,CL	5,mem=8	Multiply EA word by 2, CL times
C1	/4	db	SAL	ew,db	5,mem=8	Multiply EA word by 2, db times
DO	/7		SAR	eb,1	2,mem=7	Signed divide EA byte by 2, once
02	/7		SAR	eb,CL	5,mem=8	Signed divide EA byte by 2, CL times
CO	/7	db	SAR	eb,db	5,mem=8	Signed divide EA byte by 2, db times
01	/7		SAR	ew,1	2,mem=7	Signed divide EA word by 2, once
03	/7		SAR	ew,CL	5,mem=8	Signed divide EA word by 2, CL times
C1	/7	db	SAR	ew,db	5,mem=8	Signed divide EA word by 2, db times
DO	/5		SHR	eb,1	2,mem=7	Unsigned divide EA byte by 2, once
02	/5		SHR	eb,CL	5,mem=8	Unsigned divide EA byte by 2, CL times
CO	/5	db	SHR	eb,db	5,mem=8	Unsigned divide EA byte by 2, db times
01	/5		SHR	ew,1	2,mem=7	Unsigned divide EA word by 2, once
03	/5		SHR	ew,CL	5,mem=8	Unsigned divide EA word by 2, CL times
C1	/5	db	SHR	ew,db	5,mem=8	Unsigned divide EA word by 2, db times

* Add 1 clock to the times shown for each shift performed

FLAGS MODIFIED

Overflow (only for single-shift form), carry, zero, parity, sign

FLAGS UNDEFINED

Auxiliary carry; also overflow for multibit shifts (only).

OPERATION

SAL (or its synonym SHL) shifts the bits of the operand upward. The high-order bit is shifted into the carry flag, and the low-order bit is set to O.

SAR and SHR shift the bits of the operand downward. The low-order bit is shifted into the carry flag. The effect is to divide the operand by 2. SAR performs a signed divide: the high-order bit remains the same. SHR performs an unsigned divide: the high-order bit is set to O.

The shift is repeated the number of times indicated by the second operand, which is either an immedi- ate number or the contents of the CL register. To reduce the maximum execution time, the 80286 does not allow shift counts greater than 31. If a shift count greater than 31 is attempted, only the bottom five bits of the shift count are used. The 8086 uses all 8 bits of the shift count.

The overflow flag is set only if the single-shift forms of the instructions are used. For left shifts, it is set to 0 if the high bit of the answer is the same as the result carry flag (Le., the top two bits of the original operand were the same); it is set to 1 if they are different. For SAR it is set to 0 for all single shifts. For SHR, it is set to the high-order bit of the original operand. Neither flag bit is modified when the count value is zero.

8-97