Index-5 | Intel 80286, 80287 instruction

INDEX

NT (Nested Task Flag),	Index Registers DI, SI, 2-9
(see Flags)	Overview, 2-7
Numeric Data Processor Instructions, 3-30	Pointer Registers BP and SP, 2-9
	Segment Registers, 2-8
OF (Overflow Flag),	Status and Control, 2-14
(see Flags)	Register Direct Mode, 2-20
Offset Computation, 2-19	Register and Immediate Modes, 2-17
Operands, 2-16, 2-17	Register Indirect Mode, 2-20
OR Instruction, 2-23, 3-10, B-80	(see Addressing Modes)
OUT/OUTW, 2-23,3-29, 10-6, B-81	Reserved Interrupt Vectors,
OUTS/OUTSB/OUTSW Instruction, 3-29,	(see Interrupt Handling and Interrupt
4-1, B-82	Priorities)
	RESET, 10-7
PF (Parity Flag),	RCL Instruction, 3-14, 3-15,9-10, B-90
(see Flags)	RCR Instruction, 3-15, B-90
Pointer,	REP Prefix, 3-23,4-1,4-2, B-92
(see Data Types)	REPE Prefix, 3-24, B-92
POP Instruction, 3-3, B-83	REPNE Prefix, 3-24, B-92
POPA Instruction, 3-2, 3-5, B-85	REPNZ Prefix, 3-24
POPF Instruction, 3-26, 3-28, B-86	REPZ Prefix, 3-24
Processor Extension Error (Interrupt 6),	RET Instructon, 2-16, 3-17 - 3-19, B-94
(see Interrupt Handling and Interrupt	ROL Instruction, 3-13, B-90
Priorities)	ROR Instruction, 3-14, B-90
Processor Extension Not Available,	RPL, 7-13, 8-9, 9-6, 11-3, 11-4
(Interrupt 7),
(see Interrupt and Interrupt Priorities)	SAL Instruction, 3-11, B-97
Processor Extension Segment Overrun	SAR Instruction, 3-12, B-97
Interrupt (Interrupt 9),	SBB Instruction, 3-8, B-99
(see Interrupt and Interrupt Priorities)	SCAS Instruction, 3-4, 3-24, B-100
Protected Mode, 1-2, 1-3,6-1	SEG (Segment Override Prefix), 2-19
Protected Virtual Address Mode, 1-2,	Segment Address Translation Registers,
Protection Implementation, 7-2 - 7-4	6-9 - 6-12
Protection Mechanisms, 1-2, 1-3	Segment Descriptor, 7-10 -7-12
PUSH, 2-12, 3-2, B-87	Segment Overrun Exception (Interrupt 13),
PUSHA, 3-2, 3-3, B-85	(see Interrupt Handling and Interrupt
PUSHF, B-89	Priorities)
	Segment Selection, 2-18
Real Address Mode, 6-1, 6-2	SF (Sign Flag),
Register,	(see Flags)
Base Architecture Diagram, 2-7	SGDT Instruction, 6-12, 10-3, B-I0l
Base Register BX, 2-9, 2-17, 2-19, 2-20,	SHL Instruction, 3-11, B-97
3-1,3-7,3-8 - 3-10,3-14,3-16,	SHR Instruction, 3-12
3-17,3-22,4-7	SI Register, 2-7, 2-9, 2-11, 2-14 - 2-17,
Flags Register, 2-14, 2-15	2-19,3-17,3-23 - 3-25, 4-1
General Registers, 2-7	SmT Instruction, 10-3, B-I0l

Index-5

Image 341

Intel 80286, 80287 manual Index-5

Contents

Page Order Number Dollars ··PRICEIN Call Toll Free 800 548-4725for phone orders Infef Customer Support 80287 Programmers Reference Manual @INTELCORPORATION Organization of this Manual PrefacePage Table of Contents Extended Instruction SET Real Address Mode Chapter Memory Management and Virtual Addressing Table of Contents 10-3 10-110-4 10-5 80286/80287 Supported Data Types Flag Word Contents Dynamic Segment Relocation and Expansion of Segment Limit Code and Data Segments Assigned to a Privilege Level Reserved Exceptions and Interrupts Inter Introduction to Page Chapter Introduction to Memory Management Advanced FeaturesModes of Operation Protection Mechanisms Task Management Organization of this Book Support for Operating Systems Related Publications Inter Base Architecture Page Memory Organization and Segmentation Chapter Base Architecture 8000 r Bytes and Words in Memory Ascii ·3 /80287 Supported Data Types Base Architecture Base Architecture General Registers Registers Memory Segmentation and Segment Registers Index, Pointer, and Base Registers Real Address Mode Segment Selector Interpretation Inlel Inter Stack Operation BP Usage as a Stack Frame Base Pointer Implied Segment Usage by Index, Pointer, and Base Registers Status and Control Registers 10. Flags Register Operands Addressing Modes Memory Addressing Modes Register and Immediate Modes Segment Selection Offset Computation EASE Architecture Segment Register Selection Rules PRog~~~D BX, 51 INPUT/OUTPUTMemory Operand AddressingModes 13. Complex Addressing Modes OUT FF,AL OUTAL,FE Interrupts and Exceptions Hierarchy of Instruction Sets Interrupt Vector Assignments Real Address Mode 80186~80188 Page Basic Instruction Set Page General-Purpose Data Movement Instructions Data Movement Instructions Push Stack Manipulation Instructions Basic Instruction SET Status Flags Flag Operation with the Basic Instruction SETControl Flags Hm====i Previous Push Instructions LOW Address After Before Popa Arithmetic Instructions Basic Instruction SET Subtraction Instructions Addition Instructions Multiplication Instructions Boolean Operation Instructions Division InstructionsLogical Instructions Wordoprnd Shift and Rotate Instructions ~-i 01, I, I aI a1,1, I, I, I a1,1,1, I aI alaiI 10 01, ,1,101, 0101,1, 01 0 10 I 1I 1I 0 1I 1 1I o I o I 1 o I 1I 1111010rrG Ll 1 1 1 l 1 Control Transfer Instructions Type Conversion and No-Operation InstructionsTest and Compare Instructions Unconditional Transfer Instructions Call Instruction Conditional Transfer Instructions JGE/JNL JG/JNLEJL/JNGE JLE/JNG Software-Generated Interrupts String Manipulation Instructions and Repeat Prefixes Character Translation and String InstructionsTranslate Instruction String Movement Instructions Address Manipulation Instructions Flag Control Instructions Intel Flag Transfer Instructions BINARY-CODED Decimal Arithmetic Instructions Packed BCD Adjustment InstructionsUnpacked BCD Adjustment Instructions Machine State Instructions Trusted InstructionsTrusted and Privileged Restrictions on Popf and Iret Processor Extension Instructions Input and Output Instructions Numeric Data Processor Instructions Processor Extension Synchronization Instructions Basic Instruction SET Data Transfer Instructions Page Extended Instruction Set Page Block 1/0 Instructions Chapter Extended Instruction SET HIGH-LEVEL Instructions Formal Definition of the Enter Instruction Extended Instruction SET Variable Access in Nested Procedures 2b. Stack Frame for Procedure a 2d. Stack Frame for Procedure C at Level 3 Called from B Extended Instruction SET Page Real Address Mode Page Addressing and Segmentation Chapter Real Address Mode Real Address Mode Overlapping Segments to Save Physical Memory Real Address Mode Intr Interrupt PrioritiesNMI Reserved and Dedicated Interrupt Vectors Interrupt Procedures ESC System Initialization Processor State after ResetFlags MSW Fffoh Real Address Mode ·Memory Management Virtual Addressing Page Memory Management Overview Chapter Memory Management and Virtual Addressing Format of the Segment Selector Component Virtual Addresses Address Spaces and Task Isolation Descriptor Tables PiDPll~1 VIRTUAL-TO-PHYSICAL Address Translation PIDPLI~1 LOT Descriptor Segments and Segment Descriptors Virtual-to-Physical Address Translation Segment Address Translation Registers Memory Management Registers ~,m~ =--=--=1~~ System Address Registers Memory Management and Virtual Addressing Page Protection7 Page Chapter Protection Protection Implementation Addressing Segments of a Module within a Task Descriptor Cache Registers Protection Separation of Address Spaces LOT and GOT Access Checks LJol LIT Privilege Levels and Protection Example of Using Four Privilege Levels Privilege Usage Segment Descriptor ~~~/do I I LJ. ITI~~ DPL Data Accesses Data Access Restriction by Privilege Level Code Segment Access Pointer Privilege Stamping via Arpl NTE R Control Transfers Gates 10. Gate Descriptor Format Call Gates Se!eC!0r j ,,It Niiii INTRA-LEVEL Transfers VIA Call GateCall Gate Checks INTER-LEVEL Control Transfer VIA Call Gates Protection Stack Changes Caused by Call Gates 12. Stack Contents after an Inter-Level Call Inter-Level Return Checks Tasks and State Transitions Page Task State Segments and Descriptors Introduction Task State Segment and TSS Registers Tasks and State Transitions Task State Segment Descriptors I01 Task Switching Tasks and State Transitions Checks Made during a Task Switch CALL/INT Iret Task Linking Task Gate Descriptor Task Gates ~ASK Page Interrupts and Exceptions Page Interrupt Descriptor Table Definition Interrupt Descriptor Table An eve.! eXtern8~.~~t~~pr~~~~~1 Hardware Initiated Interrupts Interrupt Gates and Trap Gates Software Initiated Interrupts Trap/Interrupt Gate Descriptors SSFROMTSS--~.~r~------~l Trap and Interrupt Gate Checks Interrupts and Exceptions Interrupt and Gate Interactions Infer Deciding Between Task, Trap, and Interrupt Gates Scheduling Considerations Protection Exceptions and Reserved Vectors Processor Extension Segment Overrun Interrupt Double Fault InterruptInvalid OP-Code Interrupt Not Present Interrupt Invalid Task State Segment Interrupt Conditions That Invalidate the TSS Stack Fault Interrupt Additional Exceptions and Interrupts General Protection Fault Interrupt IDT Single Step Interrupt Interrupt System Control Initialization Page Descriptor Table Registers.· Chapter System Control and Initialization Local and Global Descriptor Table Definition System Control and Initialization System Control Instructions MSW Bit Functions Machine Status Word IfTS=1 ESCWait 03FFH Initialization Real Address Mode 10-8 Advanced Topics Page Conforming Code Segments Virtual Memory ManagementSpecial Segment Attributes Expand-Down Segment Expand-Down Data Segments Dynamic Segment Relocation and Expansion of Segment limit Pointer Validation Descriptor Validation Pointer Integrity RPL and the Trojan Horse Problem Multiprocessor Considerations NPX Context Switching Advanced Topics Example of NPX Context Switching Shutdown Page Appendix System Initialization Page Appendix a System Initialization System Initialization System .INITIALIZATION System Initialization Ax,.x Intel· Mov!w MovSiW AX,cl Page Appendix 80286 Instruction Set Page Appendix B 80286 Instruction SET Figure B-1. In Instruction Byte Format 80286 Instruction SET REG = Rb = Rw =Mod=OO Mod=01 Mod=10 Mod=11 BX + D8 SI + Figure B-2 Ir Instruction Byte Format 80286 U\lSTRUCTION SET Instruction Flags Modified ClocksDescription Real Address Mode Exceptions Protected Mode ExceptionsError Codes Flags Undefined #NM #UD#DF #MP #MP 9 Math Unit Protection Fault No Error Code #GP 13 General Protection Selector or Zero Error Code#MF 16 Math Fault No Error Code #NP 11 Not Present Selector Error Code #NM 7 No Math Unit Available No Error Code #TS 10 Invalid Task State Segment Selector Error Code #SS 12 Stack Fault Selector or Zero Error Code Switchtasks #UD 6 Undefined Opcode No Error CodePrivilege Level and Task Switching on 80286 Instruction SET 80286 Instruction SET AAA Ascii Adjust AL After Addition AAO AAD Ascii Adjust AX Before Division AAM D4 OA AAS AAS-ASCII Adjust AL After Subtraction ADD ADC/ ADD-Integer AdditionADC AND-Logical ARPL- Adjust RPL Field of Selector Bound rw,md noj=13 BOUND-Check Array Index Against Bounds Flags Undefined Flags ModifiedOperation Call Call Conforming Code Segment Call FARCall Nonconforming Code Segment Call to Call Gate 80286 Instruction SET Call Gate to More Privilege Protected Mode ExceptionsCall Gate to Same Privilege Call Task Gate Interrupt l3 for a word operand at offset Offffh C8W Caw-Convert Byte into Word CLC CLC-Clear Carry Flag CLO CLD-Clear Direction Flag Real Address Mode Exceptions Protected Mode ExceptionsEll-Clear Interrupt Flag 80286·INSTRUCTION SET Opcode Instruction ClocksDescription CLTS-Clear Task Switched Flag CMC CMC-Complement Carry Flag CMP CMP-Compare Two Operands Cmpsw CMPS8 CWD CWO-Convert Word to Doubleword DAA DAA-Decimal Adjust AL After Addition DAS-Decimal Adjust AL After Subtraction Opcode Structlon Clocks Description DEC-Decrement by DIVew DIV -Unsigned DivideDIVeb BP= Frameptr ENTER-Make Stack Frame for Procedure Parameters 80286 Instruction SET Protected Mode Exceptions HLT-Halt IDIV-Signed Divide Opcode Instruction Clocks Description Imul eb IMUL-Signed Multiply21,mem=24 Signed multiply rw = 21,mem=24 Signed multiply rw = EA word X imm. byte IN-Input from Port Mem=7 Increment EA word by INC INS INS/INSB/INSW-Input from Port to StringInsb Insw INT3 INT IINTO-Call to Interrupt Procedure Interrupt to Same Privilege Level InterruptInterrupt to Inner Privilege #GP, #NP, #SS, and #TS, as indicated in the list above Opcode Instruction Clock Description IRET-Interrupt ReturnIret Interrupt Return Interrupt Return to Same Level Interrupt Return on Stack #GP, #NP, or #88, as indicated in the above listing JBE JAEJGE JLE 80286 Instruction SET JMP-Jump Jump Conforming Code Segment Jump FARJump Nonconforming Code Segment Jump to Call Gate Jump Task State Segment Lahf LAHF-load Flags into AH Register Real Address Mode Exception 14,mem=16 Load highrw= Access Rights byte, selector ewInstruction SET 02 Ir LES LOS/ LES-Load Doubleword PointerLDS 80286 Instruction SET Protected Mode Exceptions Effective Address Offset LEA-load Leave LEAVE-HighLevel Procedure Exit Lgdt LGDTILIDT-Load Global/Interrupt Descriptor Table RegisterLoad m into Global Descriptor Table reg LlDT Lldt ew LLDT-Load Local Descriptor Table RegisterLoad selector ew into Local Descriptor Table Register 01 /6 LMSWew Mem=6 LMSW-Load Machine Status Word Lock LOCK-AssertBUS Lock Signal Lodsw LodsLODS8 LOOP/LOOPcond-Loop Control with CX Counter 14,mem=16 Load rw = Segment Limit, selector ew LSL-LoadSegment Limit 00 /3 LTR ew 17,mem=19 LTR-Load Task Register Mem=3 Move byte register into EA byte Opcode Instruction Clocks DescriptionMem=3 Move word register into EA word Mem=5 Move EA byte into byte register Interrupt 13 for a word operand at offset Offffh Movs MOVS/MOVSB/MOVSW-Move Data from String to StringMOVS8 Movsw MUL-Unsigned Multiplication of AL or AX NEG ew NEG-TwosComplement NegationNEG eb NOP-No Operation Not NOT-OnesComplement Negation OR- Logical Inclusive or Output byte AL to port number OX OUT OX,ALOUT OX,AX Output word AX to port number OX Outsw OutsOutsb POP SS POP Inter Popa FlAGS Undefined Popf POPF-Pop from Stack into the Flags Register Push PUSH-Push a Word onto the StackPush CS Push SS PUSHA-Push All General Registers Pushf PUSHF-Push Flags Register onto the StackPush flag~ register RCR RCLROL ROR Interrupt 13 for a word operand at offset Offffh REP Insb REP INSREP Insw REP Movs 80286 Instruction SET RET RET -Return from Procedure Return to Outer Privilege Level Return to Same Level Sahf Sahf -Store AH into Flags SHR SALSAR Interrupt 13 for a word operand at offset Offffh SBB SBB-Integer Subtraction With Borrow SCAS/SCASB/SCASW-Compare String Data 101 Sgdt /SIDT-Store Global/Interrupt Descriptor Table Register SLOT-Store Local Descriptor Table Register 103 Smsw -Store Machine Status Word 104 STe-SetCarry Flag STO STOSetDirection Flag STI STI-Set Interrupt Enable Flag Stosw Stoss 108 STR-Store Task Register00 /1 STR ew Mem=3 SUB SUB-Integer Subtraction Test TEST-Logical Compare 14,mem=16 Set ZF=1 if seg. can be read, selector ew VERR,VERW-Verifya Segment for Reading or Writing14,mem=16 111 112 Wait WAIT-Wait Until Busy Pin Is Inactive High Xchg XCHG- Exchange Memory/Register with Register Xlat mb Set AL to memory byte Osbx + unsigned Xlat -Table Look-up TranslationXlatb 115 XOR XOR-Logical Exclusive or Appendix 8086/8088 Compatibility Considerations Page Table C-1. New 80286 Interrupts Software Compatibility Considerations Pushbp MOVBP,SP XCHGBP,BP Hardware Compatibility Considerations Page 80286/80386 Software Page 80286/80386 Softvvare 80286/80386 Software Compatibility Considerations Index-1 Index Index-2 Index-3 Index-4 LODS/LODSB/LODSW, 3-24, B-69 Index-5 Index-6 Numeric Processor Extension NPX Page 80286 Microsystem AN Introduction to Related Publications Organization of This Manual Unnormals-Descendents of Denormal Operands Chapter Overview of Numeric Processing Chapter SYSTEM-LEVEL Numeric Programming 80287 Glossary of 80287 and FLOATING-POINT Terminology Index Storage Allocation Directives Tables Overview of Numeric Processing Page Performance Introduction to the 80287 Numeric Processor Extension Fxam StackO assumed Examine Overview of Numeric Processing ± Vb2 4ac Applications Upgradability PASCAL-286 FORTRAN-286 Programming Interface Numeric Data Types Hardware Interface ~r=~=~ NPX Register Stack Numeric Processor Architecture 80287 Register Set NPX Status Word Status Word Control Word Infinity, positive Inter Tag Word Format Number System Computation Fundamentals Number System Data Types and Formats Data Formats Binary Integers Rounding Control ·6. Rounding Modes Precision Control Special Numeric Values Special Computational Situations Nonnormal Real Numbers Overview of Numeric Processing Denormalization Process Unnormals-Descendents of Denormal Operands Fsqrt FrndintFIST, FISTP, Fbstp FLD Infinity Fbstp FIST, Fistp FLD, FBLD1 FILD2 FST,FSTPFprem Fsqrt +co Ftst FrndintFxtract Smallest LargestZero Smallest ......1 ---- 15 bits-----l..~1 U U ZeroU U2 Bits 16. Temporary Real Encodings Sign Biased Exponent Class NaNsSignificand· Normals Zero Divisor 16. Temporary Real Encodings ContdInvalid Operation Overview of Numeric Processing Denormalized Operand 17. Exception Conditions and Masked Responses Masked response to overflow exception earlier 17. Exception Conditions and Masked Responses Contd 11. Arithmetic Example Using Infinity Software Exception Handling Programming Numeric Applications Page Numeric Operands 80287 NPX Instruction SETCompatibility with the 8087 NPX Data Transfer Instructions FAD D destination, source Programming Numeric Applications Arithmetic Instructions Arithmetic Instructions Fsub FaddFmulp Fdiv Azimuth Fsubrp / /destination/source Fprem Condition Code Interpretation after Fprem Fcom / /source Programming Numeric Applications FabsComparison Instructions Condition Code Interpretation after Fcom Fxam Fcompp STO 1r Fptan F2XM1 FpatanFYL2X FYL2XP1 Constant Instructions Processor Control Instructions Finitifninit Fstsw AX/FNSTSW AX FSAVE/FRSTOR Memory Layout Fstenvifldenv Memory Layout Ffree destination Instruction Execution Time 12. Key to Operand TypesProgramming Numeric Applications 13. Execution Penalties Instruction Length ·14. Instruction Set Reference Data 14. Instruction Set Reference Data Contd Fdiv Programming Numeric Applications FdecstpFdivp Fdivr Fiadd DISTANCE..TRAVELLED Fiadd Pulsecount SI Ffree ST1Ficom TOOL.NPASSES Ficom BP+4.PARMCOUNT Fild Standoff DI Fidivr FrequencyFild RESPONSE.COUNT Fimul Bearing Fist BP.FACTOREDPULSES Fist OBS.COUNTSIFistp BX.ALPHACOUNT SI Fistp Correctedtime FLO 8AVEREADING FLD Reading 81.PRE88UREFldcw Controlword FLDLG2 FLOL2T FLOL2EFlopi Floz Fpatan Fmul SpeedfactorFmulp ST1,ST Fptan ·14. Instruction Set Reference Data ContdFrstor BP Fsave BP FST Correlation FST ST3FST Meanreading Fstcw Savecontrol Fstp ST2 Fstp BX.ADJUSTEDRPMFstp Totaldosage Fstp Regsave SI Fsubr Vectorsi Fsubr ST,ST1Fsubr BX.INDEX Fsubrp ST1,ST FYL2XP1 Fxch ST2FYL2X High-Level Languages Programming Facilities 15. PLlM-286 Built-In Procedures Interpretation Data Types ASM286 BIT String Shorti Nteger OFFFFFF82H HEX Must Start Status Word Record Definition TR E Q Fiaooalpha FOIVRALPHA.BETA 17. Addressing Mode ExamplesFsub Alpha SI Filo BP.BETA Sample PL/M-286 Program It *it Concurrent Processing with Emulation ·7. Sample ASM286 Program Intel Programming Numeric Applications Sample ASM286 Program Contd Instruction Synchronization Managing Concurrency Data Synchronization Synchronizing References to Shared Data Error Synchronization MOV Fsgrt System-Level Numeric Programming Page Processor Extension Data Channel Real-Address Mode and Protected Virtual-Address ModeArchitecture Processor Initialization and Control Dedicated and Reserved 1/0 LocationsSystem Initialization Recognizing. the 80287 NPX Software Routine to Recognize SYSTEM-LEVEL Numeric Programming Configuring the Numerics Environment NPX Processor State Following Initialization Initializing Handling Numeric Processing Exceptions Inter Simultaneous Exception Response Precedence of NPX Exceptions Numeric Programming Examples Page Chapter Numeric Programming Examples XAM Jump Table for Examine Routine Conditional Branching for Fxam Contd Numeric Programming Examples Proc MOV Byte PTR IBP-121, OH Fldenv Fnsave BP-941 FLOATING-POINT to Ascii Conversion Examples It116 Ebde DoeF \ii.t 4BB Lei Function. Partitioning Description of Operation Exception ConsiderationsSpecial Instructions Scaling the Value Trigonometric Calculation Examples Output Format Numeric Programming Examples Calculating Trigonometric Functions 207 Arg 0o,3 Coce 4676 Page Machine Instruction Encoding and Decoding Page REG OP-A MOD OP-S Displacement Format OP-AMOD Table A·2. Machine Instruction Decodin.9 Guide Machine Instruction Encoding and Decoding Modoo Machine Instruction Encoding and DecodingMOD01 MOD10 Table A-2. Machine Instruction Decoding Guide Contd Oreg 1REGFstswax XXXPage Appendix Compatibility Between NPX Page 80287 NPX Appendix B Compatibility Between NI NIT Appendixc· Page Appendix C Implementing the Ieee P754 Standard Additional Software to Meet the Standard Implementing the Ieee P754 Standard Page Glossary of 80287 and Floating-Point Terminology Page Glossary-1 Glossary FLOATING-POINT Terminology Inter Glossary of 80287 and FLOATING-POINT Terminology Glossary-3 Glossary of 80287 and FLOATING-POINT Terminology Glossary-4 Glossary of 80287 and FLOATING-POINT Terminology Page Index Index-2 NO-WAIT Form Index-4 Inter Inter IntJ European Sales Offices