INDEX

NT (Nested Task Flag),

Index Registers DI, SI, 2-9

(see Flags)

Overview, 2-7

Numeric Data Processor Instructions, 3-30

Pointer Registers BP and SP, 2-9

 

Segment Registers, 2-8

OF (Overflow Flag),

Status and Control, 2-14

(see Flags)

Register Direct Mode, 2-20

Offset Computation, 2-19

Register and Immediate Modes, 2-17

Operands, 2-16, 2-17

Register Indirect Mode, 2-20

OR Instruction, 2-23, 3-10, B-80

(see Addressing Modes)

OUT/OUTW, 2-23,3-29, 10-6, B-81

Reserved Interrupt Vectors,

OUTS/OUTSB/OUTSW Instruction, 3-29,

(see Interrupt Handling and Interrupt

4-1, B-82

Priorities)

 

RESET, 10-7

PF (Parity Flag),

RCL Instruction, 3-14, 3-15,9-10, B-90

(see Flags)

RCR Instruction, 3-15, B-90

Pointer,

REP Prefix, 3-23,4-1,4-2, B-92

(see Data Types)

REPE Prefix, 3-24, B-92

POP Instruction, 3-3, B-83

REPNE Prefix, 3-24, B-92

POPA Instruction, 3-2, 3-5, B-85

REPNZ Prefix, 3-24

POPF Instruction, 3-26, 3-28, B-86

REPZ Prefix, 3-24

Processor Extension Error (Interrupt 6),

RET Instructon, 2-16, 3-17 - 3-19, B-94

(see Interrupt Handling and Interrupt

ROL Instruction, 3-13, B-90

Priorities)

ROR Instruction, 3-14, B-90

Processor Extension Not Available,

RPL, 7-13, 8-9, 9-6, 11-3, 11-4

(Interrupt 7),

 

(see Interrupt and Interrupt Priorities)

SAL Instruction, 3-11, B-97

Processor Extension Segment Overrun

SAR Instruction, 3-12, B-97

Interrupt (Interrupt 9),

SBB Instruction, 3-8, B-99

(see Interrupt and Interrupt Priorities)

SCAS Instruction, 3-4, 3-24, B-100

Protected Mode, 1-2, 1-3,6-1

SEG (Segment Override Prefix), 2-19

Protected Virtual Address Mode, 1-2,

Segment Address Translation Registers,

Protection Implementation, 7-2 - 7-4

6-9 - 6-12

Protection Mechanisms, 1-2, 1-3

Segment Descriptor, 7-10 -7-12

PUSH, 2-12, 3-2, B-87

Segment Overrun Exception (Interrupt 13),

PUSHA, 3-2, 3-3, B-85

(see Interrupt Handling and Interrupt

PUSHF, B-89

Priorities)

 

Segment Selection, 2-18

Real Address Mode, 6-1, 6-2

SF (Sign Flag),

Register,

(see Flags)

Base Architecture Diagram, 2-7

SGDT Instruction, 6-12, 10-3, B-I0l

Base Register BX, 2-9, 2-17, 2-19, 2-20,

SHL Instruction, 3-11, B-97

3-1,3-7,3-8 - 3-10,3-14,3-16,

SHR Instruction, 3-12

3-17,3-22,4-7

SI Register, 2-7, 2-9, 2-11, 2-14 - 2-17,

Flags Register, 2-14, 2-15

2-19,3-17,3-23 - 3-25, 4-1

General Registers, 2-7

SmT Instruction, 10-3, B-I0l

Index-5

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