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ECQD2KCTE manual
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Contents
Main
Page
Table of Contents
1 Introduction
2 Basic Architecture
iv
3 Instruction Formats
4 Instruction Descriptions
vi
5 System Architecture and Programming Implications
6 Common PALcode Architecture
viii
7 Console Subsystem Overview 8 Input/Output Overview 9 OpenVMS Alpha
10 Digital UNIX
11 Windows NT Alpha
A Software Considerations
B IEEE Floating-Point Conformance
C Instruction Summary
D Registered System and Processor Identifiers
E Waivers and Implementation-Dependent Functionality
Page
Figures
xii
Tables
Page
Page
Page
Chapter 1
Introduction
1.1 The Alpha Approach to RISC Architecture
Alpha Is a True 64-Bit Architecture
Alpha Is Designed for Very High-Speed Imple mentations
The Alpha Approach to Byte Manipulation
The Alpha Approach to Multiprocessor Shared Memory
Alpha Instructions Include Hints for Achieving Higher Speed
PALcode Alphas Very Flexible Privileged Software Library
1.2 Data Format Overview
1.3 Instruction Format Overv iew
Figure 11: Instruct ion Format Overview
1.4 Instruction Overview
PALcode Instructions
Page
1.5 Instruction Set Characteristics
1.6 Terminology and Conventions
1.6.1 Numbering
1.6.2 Security Holes
1.6.3 UNPREDICTABLE and UNDEFINED
UNPREDICTABLE
1.6.4 Ranges and Extents
1.6.5 ALIGNED and UNALIGNED
Page
Page
Chapter 2
Basic Architecture
2.1 Addressing
2.2 Data Types
2.2.1 Byte
Figure 21: Byte Format
2.2.3 Longword
Figure 24: Quadword Format
Figure 23: Longword Format
2.2.4 Quadword
2.2.5 VAX Floating-Point Formats
2.2.5.1 F_floating
Figure 25: F_floating Datum
Figure 26: F_floating Register Format
2.2.5.2 G_floating
Figure 27: G_floating Datum
Table 21: F_floating Load Exponent Mapping (MAP_F)
Figure 28: G_floating Register Format
2.2.5.3 D_floating
Figure 29: D_floating Datum
Figure 210: D _floating Register Format
2.2.6 IEEE Floating-Point Formats
2.2.6.1 S_Floating
Figure 211: S_floating Datum
Figure 212: S_floating Register Format
Table 22: S_floating Load Exponent Mapping (MAP_S) Memory <30:23> Register <62:52>
2.2.6.2 T_floating
Figure 213: T_floating Datum
Page
Page
Figure 217: X_floating Big-Endian Datum
Figure 218: X_floating Big-Endian Register Format
2.2.7 Longword Integer Format in Floating-Poin t Unit
Figure 219: Longword Integer Datum
Figure 220: Longword Integer Floating-Register Format
2.2.8 Quadword Integer Format in Floating-Point Unit
2.2.9 Data Types with No Hardware Support
2.3 Big-Endian Addressing Support
Page
Chapter 3
Instruction Formats
3.1 Alpha Registers
3.1.1 Program Counter
3.1.2 Integer Registers
3.1.3 Floating-Point Registers
3.1.4 Lock Registers
3.1.5 Processor Cycle Counter (PCC) Register
3.1.6 Optional Registers
3.1.6.1 Memory Prefetch Registers
3.2 Notation
3.2.1 Operand Notation
3.2.2 Instruction Operand Notation
3.2.3 Operators
Page
Page
Page
3.2.4 Notation Conventions
3.3 Instruction Formats
3.3.1 Memory Instruction Format
Figure 31: M emory Instruction Format
3.3.1.1 Memory Format I nstructions with a Function Code
Figure 32: M emory Instruction with Function Code Format
3.3.1.2 Memory Format Jump Instructions
3.3.2 Branch Instruction Format
Figure 34: Operate Instruction Format
Figure 33: B ranch Instruction Format
3.3.3 Operate Instruction Format
3.3.4 Floating-Point Operate Instruction Format
Figure 35: F loating-Point Operate Instruction Format
3.3.4.1 Floating-Point Convert Instructions
3.3.4.2 Floating-Point/Integer Register Moves
3.3.5 PALcode Instruction Format
Figure 36: PALcode Instruction Format
Page
Chapter 4
Instruction Descriptions
4.1 Instruction Set Overview
4.1.1 Subsetting Rules
4.1.2 Floating-Point Subsets
4.1.3 Software Emulation Rules
4.1.4 Opcode Qualifiers
Table 41: Opcode Qualifiers Qualifier Meaning
4.2 Memory Integer Load/Store Instructions
Table 42: Memory Integer Load/Store Instructions
4.2.1 Load Address
4.2.2 Load Memory Data into Integer Register
Page
4.2.3 Load Unaligned Memory Data into Integer Register
4.2.4 Load Memory Data into Integer Register Locked
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4.2.5 Store Integer Register Data into Memory Conditional
Page
4.2.6 Store Integer Register Data into Memory
Page
4.2.7 Store Unaligned Integer Register Data into Memory
4.3 Control Instructions
Table 43: Control Instructions Summary
Page
4.3.1 Conditional Branch
4.3.2 Unconditional Branch
4.3.3 Jumps
Page
4.4 Integer Arithmetic Instructions
Count instruction (CIX) extension implemen tation note:
Table 45: Integer Arithmetic Instructions Summary
4.4.1 Longword Add
4.4.2 Scaled Longword Add
4.4.3 Quadword Add
4.4.4 Scaled Quadword Add
4.4.5 Integer Signed Compare
4.4.6 Integer Unsigned Compare
4.4.7 Count Leading Zero
4.4.8 Count Population
4.4.9 Count Trailing Zero
4.4.10 Longword Multiply
4.4.11 Quadword Multiply
4.4.12 Unsigned Quadword Multiply High
4.4.13 Longword Subtract
4.4.14 Scaled Longword Subtract
4.4.15 Quadword Subtract
4.4.16 Scaled Quadword Subtract
4.5 Logical and Shift Instructions
Table 46: Logical and Shift Instructions Summary
4.5.1 Logical Functions
4.5.2 Conditional Move Integer
Page
4.5.3 Shift Logical
4.5.4 Shift Arithm et ic
4.6 Byte Manipulation Instructions
Instruction Meanin g Descri b ed in Sect ion
Table 47: Byte-Within-Register Manipulation Instructions Summary
Page
4.6.1 Compare Byte
Page
4.6.2 Extract Byte
Page
Optimized examples:
Big-endian examples:
4.6.3 Byte Insert
Page
4.6.4 Byte Mask
Page
Page
4.6.5 Sign Extend
4.6.6 Zero Bytes
4.7 Floating-Point Instructions
4.7.1 Single-Precision Operations
4.7.2 Subsets and Fau lts
4.7.3 Definitions
Alpha finite number
Page
4.7.4 Encodings
4.7.5 Rounding Modes
VAX Rounding Modes
IEEE Rounding Modes
4.7.6 Computational Models
4.7.6.2 High-Performance VAX-Format Arithmetic
4.7.6.3 IEEE-Compliant Arithmetic
4.7.6.4 IEEE-Compliant Arithmetic Without Inexact Exception
4.7.7 Trapping Modes
Page
Page
Page
4.7.7.3 Arithmetic Trap Completion
Table 49: Summary of IEEE Trapping Modes (Continued) Trap Mode Notation Meaning
Page
Page
Page
4.7.7.5 Division by Zero (DZE) Arithmetic Trap
4.7.7.6 Overflow (OVF) Arithmetic Trap
4.7.7.7 Underflow (UNF ) Arithmetic Trap
4.7.7.8 Inexact Res ult (INE) Arithmetic Trap
4.7.7.9 Integer Overflow (IOV) Arithmetic Trap
4.7.7.10 IEEE Floating-Point Trap Disable Bits
4.7.7.11 IEEE Denormal Control Bits
4.7.8 Floating-Point Control Register (FPCR)
Figure 41: F loating-Point Control Register (FPCR) Format
DYN IEEE Rounding Mode Selected
Page
4.7.8.1 Access ing the FPCR
4.7.8.2 Default Values of the FPCR
4.7.8.3 Saving and Restoring the FPCR
Software Notes:
4.7.9 Floating-Point Instruction Function Field Format
Figure 42: F loating-Point Instruction Function Field
Table 412: IEEE Floating-Point Function Field Bit Summary Bits Field Meaning
Table 412: IEEE Floating-Point Function Field Bit Summary (Continued) Bits Field Meaning
Table 413: VAX Floating-Point Function Field Bit Summary Bits Field Meaning
4.7.10 IEEE Standard
4.7.10.1 Conversion of NaN and Infinity Values
Table 413: VAX Floating-Point Function Field Bit Summary (Continued) Bits Field Meaning
4.7.10.2 Copying NaN Values
4.7.10.3 Generating NaN Values
4.7.10.4 Propagating NaN Values
4.8 Memory Format Floating-Point Instr uctions
Table 414: Memory Format Floating-Point Instructions Summary
4.8.1 Load F_floating
4.8.2 Load G_floating
4.8.3 Load S_floating
4.8.4 Load T_floating
4.8.5 Store F_floating
4.8.6 Store G_floating
4.8.7 Store S_floating
4.8.8 Store T_floating
4.9 Branch Format Floating-Point Instructions
Table 415: Floating-Point Branch Instructions Summary
4.9.1 Conditional Branch
Page
4.10 Floating-Point Operate Format Instructio ns
Floating-point convert and square-root (FIX) extension implementati on no te:
Table 416: Floating-Point Operate Instructions Summary
Bit and FPCR Operations:
Arithmetic Operations
Table 416: Floating-Point Operate Instructions Summary (Continued)
Page
4.10.1 Copy Sign
4.10.2 Convert Integer to Integer
4.10.3 Floating-Point Conditional Move
Page
4.10.4 Move from/to Floating-Point Control Register
4.10.5 VAX Floating Add
4.10.6 IEEE Floating Add
4.10.7 VAX Floating Compare
4.10.8 IEEE Floating Compare
4.10.9 Convert VAX Floating to Integer
4.10.10 Convert Integer to VAX Floating
4.10.11 Convert VAX Floating to V AX Floating
4.10.12 Convert IEEE Floating to Integer
4.10.13 Convert Integer to IEEE Floating
4.10.14 Convert IEEE S_Floating to IEEE T_Floating
4.10.15 Convert IEEE T_Floating to IEEE S_Floating
4.10.16 VAX Floating Divide
4.10.17 IEEE Floating Divide
4.10.18 Floating-Point Register to Integer Register Move
4.10.19 Integer Register to Floating-Point Register Move
Page
4.10.20 VAX Floating Multiply
4.10.21 IEEE Floating Multiply
4.10.22 VAX Floating Square Root
4.10.23 IEEE Floating Square Root
4.10.24 VAX Floating Subtract
4.10.25 IEEE Floating Subtract
4.11 Miscellaneous Instructions
Table 417: Miscellaneous Instructions Summary
4.11.1 Architecture Mask
Page
4.11.2 Call Privileged Architecture Library
4.11.3 Evict Data Cache Block
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4.11.4 Exception Barrier
4.11.5 Prefetch Data
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4.11.6 Implementation Version
4.11.7 M emory Barrier
4.11.8 R ead Processor Cycle Counter
4.11.9 Trap Barrier
4.11.10 Write Hint
Page
4.11.11 Write Memory Barrier
Processor i Processor j
4.12 VAX Compatibility Instructions
4.12.1 VAX Compatibility Instructions
4.13 Multimedia (Graphics and Video) Support
4.13.1 Byte and Word Minimum and Maximum
None
Page
4.13.2 Pixel Error
4.13.3 Pack Bytes
4.13.4 Unpack Bytes
Chapter 5
System Architecture and Programming Implications
5.1 Introduction
5.2 Physical Address Space Characteristics
5.2.1 Coherency of Memory Access
Software/Hardware Note:
5.2.2 Granularity of Memory Access
5.2.3 Width of Memory Access
5.2.4 Memory-Like and Non-Memory-Like Behavior
Hardware/Software Coordination Note:
5.3 Translation Buffers and Virtual Caches
5.4 Caches and Write Buffers
Page
5.5 Data Sharing
5.5.1 Atomic Change of a Single Datum
5.5.2 Atomic Update of a Single Datum
5.5.3 Atomic Update of Data Structures
5.5.4 Ordering Considerations for Shared Data Structures
5.6 Read/Write Ordering
5.6.1 Alpha Shared Memory Model
Page
5.6.1.1 Architectural Definition of Processor Issue Sequence
5.6.1.2 Definition of Before and After
5.6.1.3 Definition of Processor Issue Constraints
Table 51: Processor Issue Constraints
5.6.1.4 Definition of Location Access Constraints
5.6.1.5 Definition of Visibility
5.6.1.6 Definition of Storage
5.6.1.7 Definition of Dependence Constraint
5.6.1.8 Definition of Load-Locked and Store-Conditional
5.6.1.9 Timeliness
5.6.2 Litmus Tests
5.6.2.1 Litmus Test 1 (Impossible Sequence)
5.6.2.2 Litmus Test 2 (Impossible Sequence)
5.6.2.3 Litmus Test 3 (Impossible Sequence)
Pi Pj Pk
Page
5.6.2.7 Litmus Test 7 (Impossible Sequence)
5.6.2.8 Litmus Test 8 (Impossible Sequence)
5.6.2.9 Litmus Test 9 (Impossible Sequence)
5.6.2.10 Litmus Test 10 (Sequence Okay)
5.6.2.11 Litmus Test 11 (Impossible Sequence)
5.6.3 Implied Barriers
5.6.4 Implications for Software
5.6.4.1 Single Processor Dat a Stream
5.6.4.2 Sin gle Processor Instruction Stream
5.6.4.4 Mult iprocessor Instruction Stream (Including Single Processor with DMA I/O)
5.6.4.5 Multi processor Context Switch
Page
5.6.4.6 Mult iprocesso r Send/Rece ive Interrupt
5.6.4.7 Implications for Memory Mapped I/O
5.6.4.8 Multiple Processors Writing to a Single I/O De vice
5.6.5 Implications for Hardware
5.7 Arithmetic Traps
Chapter 6
Common PALcode Architecture
6.1 PALcode
6.2 PALcode Instructions and Functions
6.3 PALcode Environment
6.4 Special Functions Required for PALcode
6.5 PALcode Effects on System Code
6.6 PALcode Replacement
6.7 Required PALcode Instructions
Page
6.7.1 Drain Aborts
6.7.2 Halt
6.7.3 Instruction Memory Barrier
Chapter 7
Console Subsystem Overview
Page
Chapter 8
Input/Output Overview
Page
Chapter 9
OpenVMS Alpha
9.1 Unprivileged OpenVMS Alpha PALcode
Page
Page
Page
Page
Page
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9.2 Privileged OpenVMS Alpha Palco de
Page
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Chapter 10
Digital UNIX
10.1 Unprivileged Digital UNIX PALcode
10.2 Privileged Digital UNIX PALcode
Page
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Chapter 11
Windows NT Alpha
11.1 Un privileged Windows NT Alpha PALcode
Table 111 : Unprivileged Windows NT Alpha PALcode Instruction Summary
11.2 Privileged Windows NT Alpha PALcode
Table 111 : Unprivileged Windows NT Alpha PALcode Instruction Summary
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Appendix A
Software Considerations
A.1 Hardware-Software Compact
A.2 Instruction-Stream Considerations
A.2.1 Instruction Alignment
A.2.2 Branch Prediction and Minimizing Branch-Taken Factor of 3
Figure A1: Br anch-Format BSR and BR Opcodes
Figure A2: Memory-Format JSR Instruction
A.2.3 Improving I-Stream Density Factor of 3
A.2.4 Instruction Scheduling Factor of 3
A.3 Data-Stream Considerations
A.3.1 Data Alignment Factor of 10
A.3.2 Shared Data in Multiple Processors Factor of 3
A.3.3 Avoiding Cache/TB Conflicts Factor of 1
Figure A3: Bad Allocation in Cache
Figure A4: Better Allocation in Cache
Figure A5: Be st Allocation in Cache
A.3.4 Sequential Read/Write Factor of 1
A.3.5 Prefetching Factor of 3
Table A1: Cache Block Prefetching Type Instructions Operation
A.4 Code Sequences
A.4.1 Aligned Byte/Word (Within Register) Memory Accesses
Table A1: Cache Block Prefetching Type Instructions Operation
A.4.2 Division
A.4.3 Byte Swap
A.4.4 Stylized Code Forms
A.4.4.1 NOP
A.4.4.2 Clear a Register
A.4.4.3 Load Literal
A.4.4.4 Register-to-Register Move
A.4.4.5 Negate
A.4.4.6 NOT
A.4.4.7 Booleans
A.4.5 Exceptions and Trap Barriers
A.4.6 Pseudo-Operations (Stylized Code Forms)
Encoding
Software Considerations
Encoding
A.5 Timing Considerations: Atomic Sequences
Appendix B
IEEE Floating-Point Conformance
B.1 Alpha Choices for IEEE Options
Page
B.2 Alpha Support for OS Completion Handlers
B.2.1 IEEE Floating-Point Control (FP_C) Quadword
Figure B1: IEEE Floating-Point Control (FP_C) Quadword
Table B1: Floating-Point Control (FP_C) Quadword Bit Summary Bit Description
B.3 Mapping to IEEE Standard
Table B1: Floating-Point Control (FP_C) Quadword Bit Summary (Continued) Bit Description
Figure B2: IEEE T rap Handling Behavior
Table B2: IEEE Floating-Point Trap Handling
OS Completion
User
ADDx SUBx INPUT Exceptions:
ADDx SUBx OUTPUT Exceptions:
Table B2: IEEE Floating-Point Trap Handling (Contin ued)
OS Completion
User
CMPTLT CMPTLE INPUT Exceptions:
CVTfi INPUT Exceptions:
CVTff OUTPUT Exceptions:
Table B2: IEEE Floating-Point Trap Handling (Contin ued)
OS Completion
User
Page
Page
Appendix C
Instruction Summary
Symbol Opcode
C.1 Common Architecture Instruction Summary
Table C1: Instruction Format and Opcode Notation Instruction Format Format
Notation Meaning
Table C2: Common Architecture Instructions
Page
Page
Page
C.2 IEEE Floating-Point Instructions
Table C3: IEEE Floating-Point Instruction Function Codes
Programming Note:
Table C3: IEEE Floating-Point Instruction Function Codes (Continued)
C.3 VAX Floating-Point Instructions
Table C4: VAX Floating-Point Instruction Function Codes None /C /U /UC /S /SC /SU /SUC
None /C /V /VC /S /SC /SV /SVC
C.4 Independent Floating-Point Instructions
C.5 Opcode Summary
Table C5: Independent Floating-Point Instruction Function Codes None /V /SV
Table C6: Opcode Summary
Table C7: Key to Opcode Summary Symbol Meaning
C.6 Common Architecture Opcodes in Numerical Order
Table C8: Common Architecture Opcodes in Numerical Order
Page
Page
Instruction Summary
C.7 OpenVMS Alpha PALcode Instruction Summary
Table C9: OpenVMS Alpha Unprivileged PALcode Instructions Mnemonic Opcode Description
Table C10: OpenVMS Alpha Privileged PALcode Instructions
C.8 DIGITAL UNIX PALcode Instruction Summary
Table C11: DIGITAL UNIX Unprivileged PALcode Instructions
Table C12: DIGITAL UNIX Privileged PALcode Instructions
C.9 Windows NT Alpha Instruction Summary
Table C13: Windows NT Alpha Unprivileged PALcode Instructions
Table C14: Windows NT Alpha Privileged PALcode instructions
C.10 PALcode Opcodes in Numerical Order
Alpha
Alpha
C.11 Requ ired PALcode Opcodes
C.12 Opcodes Reserved to PALcode
C.13 Opcodes Reserved to Compaq
Programming Note:
C.14 Unused Function Code Behavior
Table C18: Opcodes Reserved for Compaq Mnemonic Mnemonic Mnemonic
C.15 ASCII Character Set
Table C19: ASCII Character Set Char Hex
Code Char Hex
Appendix D
Registered System and Processor Identifiers
D.1 Processor Type Assignments
Table D1: Processor Type Assignments Major Type Minor Type
D.2 PALcode Variation Assignments
Table D2: PALcode Variation Assignments Token PALcode Type Summary Table
Table D1: Processor Type Assignments (Continued) Major Type Minor Type
D.3 Architecture Mask and Implementation Values
Table D3: AMASK Bit Assignments Bit Meaning
Table D4: IMPLVER Value Assignments Val ue M ea ni n g
Table D2: PALcode Variation Assignments Token PALcode Type Summary Table
Page
Appendix E
Waivers and Implementation-Dependent Functionality
E.1 Waivers
E.1.1 DECchip 21064, DECchip 21066, and DECchip 21068 IEEE Divide Instruction Violation
E.1.2 DECchip 21064, DECchip 21066, and DECchip 21068 Write Buffer Violation
E.1.3 DECchip 21264 LDx_L/STx_C with WH64 Violation
E.2 Implementation-Specific Functionality
E.2.1 DECchip 21064/21066/21068 Performance Monitoring
E.2.1.1 DECchip 21064/21066/21068 Performance Monitor Interrupt Mechanism
Page
Select desired events (mux_ctl)
Select performance monitoring options
Page
Page
E.2.2 DECchip 21164/21164PC Performance Monitoring
E.2.2.1 Performance Monitor Interrupt Mechanism
E.2.2.2 Windows NT Alpha Functions and Argument
Table E3: Bit Summary of PMCTR Register for Windows NT Alpha
Page
Enable performance monitoring; start the counters from zero
Disable performance monitoring; do not reset counters
Select desired events (MUX_SELECT)
Select Processor Mode options
Select interrupt frequencies
Read the counters
Page
Table E7: 21164 Select Desired Events for OpenVMS Alpha and DIGITAL UNIX
Table E8: 21164PC Select Desired Events for OpenVMS Alpha and DIGI TAL UNIX
Page
Table E10: 21164/21164PC Select Desired Frequencies for OpenVMS Alpha and DIGITAL UNIX
Bits Meaning When Set
Page
Table E14: 21164/21164PC Counter 2 (PCSEL2) Event Selection
Table E13: 21164/21164PC Counter 1 (PCSEL1) Event Selection (Continued)
Table E15: 21164 CBOX1 Event Selection
Val ue M ea ni n g
Table E16: 21164 CBOX2 Event Selection
Table E17: 21164PC PM0_MUX Event Selection
Table E18: 21164PC PM1_MUX Event Selection
E.2.3 21264 Performance Monitoring
E.2.3.1 Performance Monitor Interrupt Mechanism
E.2.3.2 Windows NT Alpha Functions and Argument
Table E19: Bit Summary of PCTR_CTL Register for Windows NT Alpha
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Index
A
B
C
D
E
F
G
H
I
J
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z