Compaq ECQD2KCTE manual Invalid Operation INV Arithmetic Trap

Table 4–10: Trap Shadow Length Rules (Continued)

Floating-Point	Trap Shadow Extends Until Any of the Following
Instruction Group	Occurs:

Floating-point SQRTx

•Encountering a CALL_PAL, EXCB, or TRAPB instruction.

•The result is consumed by any instruction.

•The result of a subsequent SQRTx instruction is con- sumed by any instruction.

†The length of four instructions is a conservative estimate of how far the trap shadow may extend past a consuming floating-point STx instruction. The length of two instructions is a conservative estimate of how far the trap shadow may extend after a subsequent float- ing-point operate instruction is consumed by a floating-point STx instruction. Compilers can make a more precise estimate by consulting the DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware Reference Manual, EC-QD2RA-TE.

4.7.7.4Invalid Operation (INV) Arithmetic Trap

An invalid operation arithmetic trap is signaled if an operand is a non-finite number or if an operand is invalid for the operation to be performed. (Note that CMPTxy does not trap on plus or minus infinity.) Invalid operations are:

•Any operation on a signaling NaN.

•Addition of unlike-signed infinities or subtraction of like-signed infinities, such as (+infinity + –infinity) or (+infinity – +infinity).

•Multiplication of 0∗infinity.

•IEEE division of 0/0 or infinity/infinity.

•Conversion of an infinity or NaN to an integer.

•CMPTLE or CMPTLT when either operand is a NaN.

•SQRTx of a negative non-zero number.

The instruction cannot disable the trap and, if the trap occurs, an UNPREDICTABLE value is stored in the result register. However, under some conditions, the FPCR can dynamically dis- able the trap, as described in Section 4.7.7.10, producing a correct IEEE result, as described in Section 4.7.10.

IEEE-compliant system software must also supply an invalid operation indication to the user for x REM 0 and for conversions to integer that take an integer overflow trap.

If an implementation does not support the DZED (division by zero disable) bit, it may respond to the IEEE division of 0/0 by delivering a division by zero trap to the operating system, which IEEE compliant software must change to an invalid operation trap for the user.

4–76Alpha Architecture Handbook