Floating-Point Operate Instructions
The
In addition to the operations found in conventional RISC architectures, Alpha includes condi- tional move instructions for avoiding branches and merge sign/exponent instructions for simple field manipulation.
The arithmetic trap enables and rounding mode are encoded in the function field of each in stru cti on , rath er t han kep t i n g lo bal stat e bi ts . Th at mak es i t eas ier to pi pel in e implementations.
1.5 Instruction Set Characteristics
Alpha instruction set characteristics are as follows:
•All instructions are 32 bits long and have a regular format.
•There are 32 integer registers (R0 through R31), each 64 bits wide. R31 reads as zero, and writes to R31 are ignored.
•All integer data manipulation is between integer registers, with up to two variable regis- ter source operands (one may be an
•There are 32
•All
•Instructions can move data in an integer register file to a
•All memory reference instructions are of the load/store type that moves data between registers and memory.
•There are no branch condition codes. Branch instructions test an integer or floating- point register value, which may be the result of a previous compare.
•Integer and logical instructions operate on quadwords.
•
•A minimal number of VAX compatibility instructions are included.
1.6Terminology and Conventions
The following sections describe the terminology and conventions used in this book.