In the case of LDQ and LDL, the source operand is fetched from memory,
In the case of LDWU and LDBU, the source operand is fetched from memory,
In all cases, if the data is not naturally aligned, an alignment exception is generated.
Notes:
•The word or byte that the LDWU or LDBU instruction fetches from memory is placed in the low (rightmost) word or byte of Ra, with the remaining 6 or 7 bytes set to zero.
•Accesses have byte granularity.
•For
•No sparse address space mechanisms are allowed with the LDWU and LDBU instruc- tions.
Implementation Notes:
•The LDWU and LDBU instructions are supported in hardware on Alpha implementa- tions for which the AMASK instruction returns bit 0 set. LDWU and LDBU are sup- ported with software emulation in Alpha implementations for which AMASK does not return bit 0 set. Software emulation of LDWU and LDBU is significantly slower than hardware support.
•Depending on an address space region’s caching policy, implementations may read a (partial) cache block in order to do word/byte stores. This may only be done in regions that have
•Implementations are expected to provide sufficient
Instruction Descriptions