Compaq ECQD2KCTE manual Computational Models, VAX Rounding Mode Instruction Notation

The following tables summarize the floating-point rounding modes:

VAX Rounding Mode	Instruction Notation
Normal rounding	(No qualifier)
Chopped	/C
IEEE Rounding Mode	Instruction Notation
Normal rounding	(No qualifier)
Dynamic rounding	/D
Plus infinity	/D and ensure that FPCR<DYN> = ‘11’
Minus infinity	/M
Chopped	/C

4.7.6 Computational Models

The Alpha architecture provides a choice of floating-point computational models.

There are two computational models available on systems that implement the VAX float- ing-point subset:

•VAX-format arithmetic with precise exceptions

•High-performance VAX-format arithmetic

There are three computational models available on systems that implement the IEEE float- ing-point subset:

•IEEE compliant arithmetic

•IEEE compliant arithmetic without inexact exception

•High-performance IEEE-format arithmetic

4.7.6.1VAX-Format Arithmetic with Precise Exceptions

This model provides floating-point arithmetic that is fully compatible with the floating-point arithmetic provided by the VAX architecture. It provides support for VAX non-finites and gives precise exceptions.

This model is implemented by using VAX floating-point instructions with the /S, /SU, and /SV trap qualifiers. Each instruction can determine whether it also takes an exception on underflow or integer overflow. The performance of this model depends on how often computations involve non-finite operands. Performance also depends on how an Alpha system chooses to trade off implementation complexity between hardware and operating system completion han- dlers (see Section 4.7.7.3).

Instruction Descriptions 4–67