An implementation may choose not to take an INV trap for a valid IEEE operation that involves denormal operands if:
•The instruction is modified by any valid qualifier combination that includes the /S (exception completion) qualifier.
•The implementation supports the DNZ (denormal operands to zero) bit and DNZ is set.
•The instruction produces the result and exceptions required by Section 4.7.10, as modi- fied by the DNZ bit described in Section 4.7.7.11.
An implementation may choose not to take an INV trap for a valid IEEE operation that involves denormal operands, and direct hardware implementation of denormal arithmetic is permitted if:
•The instruction is modified by any valid qualifier combination that includes the /S (exception completion) qualifier.
•The implementation supports both the DNOD (denormal operand exception disable) bit and the DNZ (denormal operands to zero) bit and DNOD is set while DNZ is clear.
•The instruction produces the result and exceptions required by Section 4.7.10, possibly modified by the UDNZ bit described in Section 4.7.7.11.
Regardless of the setting of the INVD (invalid operation disable) bit, the implementation may choose not to trap on valid operations that involve quiet NaNs and infinities as operands for IEEE instructions that are modified by any valid qualifier combination that includes the /S (exception completion) qualifier.
4.7.7.5 Division by Zero (DZE) Arithmetic Trap
A division by zero arithmetic trap is taken if the numerator does not cause an invalid operation trap and the denominator is zero.
The instruction cannot disable the trap and, if the trap occurs, an UNPREDICTABLE value is stored in the result register. However, under some conditions, the FPCR can dynamically dis- able the trap, as described in Section 4.7.7.10, producing a correct IEEE result, as described in Section 4.7.10.
If an implementation does not support the DZED (division by zero disable) bit, it may respond to the IEEE division of 0/0 by delivering a division by zero trap to the operating system, which IEEE compliant software must change to an invalid operation trap for the user.
4.7.7.6 Overflow (OVF) Arithmetic Trap
An overflow arithmetic trap is signaled if the rounded result exceeds in magnitude the largest finite number of the destination format.
The instruction cannot disable the trap and, if the trap occurs, an UNPREDICTABLE value is stored in the result register. However, under some conditions, the FPCR can dynamically dis- able the trap, as described in Section 4.7.7.10, producing a correct IEEE result, as described in Section 4.7.10.
Instruction Descriptions
