The DECchip 21264 varies from that description, with regard to the WH64 instruction, as follows:
If any other memory access (ECB, LDx, LDQ_U, STx, STQ_U) is executed on the given processor between the LDx_L and the STx_C, the sequence above may always fail on some implementations; hence, no useful program should do this.
If a WH64 memory access is executed on any given 21264 processor between the LDx_L and STx_C, and:
–The WH64 access is to the same aligned
–No CALL_PAL REI, rei, or rfe instruction has been executed since the
then, the
E.2 Implementation-Specific Functionality
The following functionality, although a documentated part of the Alpha architecture, is imple- mented in a manner that is specific to the particular hardware implementation.
E.2.1 DECchip 21064/21066/21068 Performance Monitoring
Note:
All functions, arguments, and descriptions in this section apply to the DECchip 21064/21064A, 21066/21066A, and 21068/21068A.
PALcode instructions control the DECchip 21064/21066/21068
The instruction arguments and results are described in the following sections. The scratch reg- ister usage is operating system specific.
Two
The two counters can be switched independently. There is no hardware support for reading, writing, or resetting the counters. The only way to monitor the counters is to enable them to cause an interrupt on overflow.
Waivers and