Compaq ECQD2KCTE manual Instruction Formats

	2.3	Big-Endian Addressing Support	2–13
3	Instruction Formats
	3.1	Alpha Registers	3–1
	3.1.1	Program Counter	3–1
	3.1.2	Integer Registers	3–1
	3.1.3	Floating-Point Registers	3–2
	3.1.4	Lock Registers	3–2
	3.1.5	Processor Cycle Counter (PCC) Register	3–3
	3.1.6	Optional Registers	3–3
	3.1.6.1	Memory Prefetch Registers	3–3
	3.1.6.2	VAX Compatibility Register	3–3
	3.2	Notation	3–3
	3.2.1	Operand Notation	3–4
	3.2.2	Instruction Operand Notation	3–5
	3.2.2.1	Operand Name Notation	3–5
	3.2.2.2	Operand Access Type Notation	3–5
	3.2.2.3	Operand Data Type Notation	3–6
	3.2.3	Operators	3–6
	3.2.4	Notation Conventions	3–10
	3.3	Instruction Formats	3–10
	3.3.1	Memory Instruction Format	3–11
	3.3.1.1	Memory Format Instructions with a Function Code	3–11
	3.3.1.2	Memory Format Jump Instructions	3–12
	3.3.2	Branch Instruction Format	3–12
	3.3.3	Operate Instruction Format	3–12
	3.3.4	Floating-Point Operate Instruction Format	3–13
	3.3.4.1	Floating-Point Convert Instructions	3–14
	3.3.4.2	Floating-Point/Integer Register Moves	3–14
	3.3.5	PALcode Instruction Format	3–14
4	Instruction Descriptions
	4.1	Instruction Set Overview	4–1
	4.1.1	Subsetting Rules	4–2
	4.1.2	Floating-Point Subsets	4–2
	4.1.3	Software Emulation Rules	4–3
	4.1.4	Opcode Qualifiers	4–3
	4.2	Memory Integer Load/Store Instructions	4–4
	4.2.1	Load Address	4–5
	4.2.2	Load Memory Data into Integer Register	4–6
	4.2.3	Load Unaligned Memory Data into Integer Register	4–8
	4.2.4	Load Memory Data into Integer Register Locked	4–9
	4.2.5	Store Integer Register Data into Memory Conditional	4–12
	4.2.6	Store Integer Register Data into Memory	4–15
	4.2.7	Store Unaligned Integer Register Data into Memory	4–17
	4.3	Control Instructions	4–18
	4.3.1	Conditional Branch	4–20
	4.3.2	Unconditional Branch	4–21
	4.3.3	Jumps	4–22
	4.4	Integer Arithmetic Instructions	4–24
	4.4.1	Longword Add	4–25
	4.4.2	Scaled Longword Add	4–26
	4.4.3	Quadword Add	4–27
	4.4.4	Scaled Quadword Add	4–28

iv