Compaq ECQD2KCTE manual Index-2

programming implications for, 5–30TRAPB instruction with, 4–144underflow, 4–78 ,4–81underflow to zero, disabling, 4–80underflow, disabling, 4–80underflow, enabling, B–6underflow, status of, B–5

ASCII character set, C–22

Atomic access, 5–3

Atomic operations

accessing longword datum, 5–2accessing quadword datum, 5–2updating shared data structures, 5–7

using load locked and store conditional, 5–7Atomic sequences, A–16

B

BEFORE, defined for memory access, 5–12

BEQ instruction, 4–20

BGE instruction, 4–20

BGT instruction, 4–20

BIC instruction, 4–42

Big-endian addressing, 2–13

byte operation examples, 4–54byte swapping for, A–11extract byte with, 4–51insert byte with, 4–55

load F_floating with, 4–91

load long/quad locked with, 4–9load S_floating with, 4–93mask byte with, 4–57

store byte/word with, 4–15store F_floating with, 4–95

store long/quad conditional with, 4–12store long/quad with, 4–15

store S_floating with, 4–97Big-endian data types, X_floating, 2–10

BIS instruction, 4–42

BLBC instruction, 4–20

BLBS instruction, 4–20

BLE instruction, 4–20

BLT instruction, 4–20

BNE instruction, 4–20

Boolean instructions, 4–41logical functions, 4–42

Boolean stylized code forms, A–13

BPT (PALcode) instruction required recognition of, 6–4

bpt (PALcode) instruction required recognition of, 6–4

BR instruction, 4–21

Branch instructions, 4–18

backward conditional, 4–20conditional branch, 4–20floating-point, summarized, 4–99format of, 3–12

forward conditional, 4–20

opcodes and format summarized, C–1unconditional branch, 4–21

See also Control instructions Branch prediction model, 4–18

Branch prediction stack,with BSR instruction, 4–21

BSR instruction, 4–21

BUGCHK (PALcode) instruction required recognition of, 6–4

bugchk (PALcode) instruction required recognition of, 6–4

Byte data type, 2–1atomic access of, 5–3

Byte manipulation, 1–2

Byte manipulation instructions, 4–47

Byte swapping, A–11

BYTE_ZAP(x,y) operator, 3–7

C

/C opcode qualifier

IEEE floating-point,4–67VAX floating-point,4–67

C opcode qualifier, 4–67

Cache coherency

barrier instructions for, 5–25defined, 5–2

in multiprocessor environment, 5–6Caches

design considerations, A–1I-stream considerations, A–4

MB and IMB instructions with, 5–25requirements for, 5–5

translation buffer conflicts, A–6with powerfail/recovery, 5–5

CALL_PAL (call privileged architecture library) instruction, 4–135

CASE operator, 3–8

Causal loops, 5–15

CFLUSH (PALcode) instruction

ECB compared with, 4–138

Index–2