The DECchip 21064, DECchip 21066, and DECchip 21068 implementations differ from the above specification in handling the Inexact condition for the IEEE DIVS and DIVT instruc- tions in two ways:
1.The DIVS and DIVT instructions with the /Inexact modifier trap unconditionally and report the INE exception in the EXC_SUM register (except for NaN, infinity, and denormal inputs that result in INVs). This allows for a software calculation to deter- mine the correct INE status.
2.The FPCR <INE> bit is never set by DIVS or DIVT. This is because the DECchip 21064, DECchip 21066, and DECchip 21068 do not include hardware to determine that particular exactness.
E.1.2 DECchip 21064, DECchip 21066, and DECchip 21068 Write Buffer Violation
The DECchip 21064, DECchip 21066, and DECchip 21068 CPUs can be made to violate the architecture by, under one contrived case, indefinitely delaying a buffered
Note:
The DECchip 21064A, DECchip 21066A, and DECchip 21068A CPUs are compliant and require no waiver. The DECchip 21164 is also compliant.
The CPUs in violation can send a buffered write
1.The write buffer contains at least two valid entries.
2.The write buffer contains one valid entry and 256 cycles have elapsed since the execu- tion of the last write.
3.The write buffer contains an MB or STx_C instruction.
4.A load miss hits an entry in the write buffer.
The write can be delayed indefinitely under condition 2 above, when there is an indefinite stream of writes to addresses within the same aligned
E.1.3 DECchip 21264 LDx_L/STx_C with WH64 Violation
The DECchip 21264 violates the architected relationship between the LDx_L and STx_C instructions when an intervening WH64 instruction is executed.
As specified in Section 4.2.4:
If any other memory access (ECB, LDx, LDQ_U, STx, STQ_U, WH64) is executed on the given processor between the LDx_L and the STx_C, the sequence above may always fail on some implementations; hence, no useful program should do this.
