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Compaq ECQD2KCTE manual Store Unaligned Integer Register Data into Memory, Stqu

Models: ECQD2KCTE

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4.2.7 Store Unaligned Integer Register Data into Memory

Format:

STQ_U

Ra.rq,disp.ab(Rb.ab)

!Memory format

Operation:

va ← {{Rbv + SEXT(disp)} AND NOT 7} (va)<63:0> ← Rav<63:0>

Exceptions:

Access Violation

Fault on Write

Translation Not Valid

Instruction mnemonics:

STQ_U

Store Unaligned Quadword from Register to Memory

Qualifiers:

None

Description:

The virtual address is computed by adding register Rb to the sign-extended 16-bit displace- ment, then clearing the low order three bits. The Ra operand is written to memory at this address.

Instruction Descriptions 4–17

Image 73

Compaq ECQD2KCTE manual Store Unaligned Integer Register Data into Memory, Stqu

Contents

Alpha Architecture Handbook October Table of Contents Instruction Formats Page 10.19 Integer Register to Floating-Point Register Move System Architecture and Programming Implications Digital Unix Ieee Floating-Point Conformance Index Figures Tables Xiii Xiv Preface Page Alpha Approach to Risc Architecture ChapterAlpha Is a True 64-Bit Architecture Alpha Is Designed for Very High-Speed ImplementationsAlpha Approach to Multiprocessor Shared Memory Alpha Approach to Byte ManipulationAlpha Instructions Include Hints for Achieving Higher Speed PALcode Alpha’s Very Flexible Privileged Software LibraryAlpha and Programming Languages Data Format OverviewInstruction Overview Instruction Format OverviewPALcode Instructions Load/Store Instructions Branch InstructionsInteger Operate Instructions Terminology and Conventions Instruction Set CharacteristicsFloating-Point Operate Instructions Security Holes NumberingUnpredictable and Undefined Aligned and Unaligned Ranges and ExtentsUnaligned Read As Zero RAZ Must Be Zero MBZShould Be Zero SBZ Ignore IGNPage Data Types AddressingByte WordQuadword LongwordFfloating VAX Floating-Point FormatsGfloating Ffloating Load Exponent Mapping MapfDfloating Gfloating Register FormatIeee Floating-Point Formats Sfloating Load Exponent Mapping Maps Memory Register SFloating13 Tfloating Datum TfloatingXFloating 14 Tfloating Register FormatXFloating Big-Endian Formats 15 Xfloating Datum17 Xfloating Big-Endian Datum Longword Integer Format in Floating-Point UnitData Types with No Hardware Support Quadword Integer Format in Floating-Point Unit23 Little-Endian Byte Addressing Big-Endian Addressing Support14Alpha Architecture Handbook Program Counter Alpha RegistersInteger Registers Implementation noteLock Registers Floating-Point RegistersProcessor Cycle Counter PCC Register NotationOptional Registers Memory Prefetch RegistersOperand Notation Meaning Operand NotationOperand Value Notation Meaning Expression Operand Notation MeaningOperand Access Type Notation Meaning Operand Access Type NotationInstruction Operand Notation Operand Name NotationOperand Data Type Notation OperatorsOperand Data Type Notation Meaning Operators MeaningBit concatenation DIV CaseLoadlocked Physicaladdress NotPriorityencode LTUNotation Conventions Instruction FormatsSoftware Note XORMemory Format Instructions with a Function Code Memory Instruction FormatOperate Instruction Format Branch Instruction FormatMemory Format Jump Instructions Floating-Point Operate Instruction Format Floating-Point Operate Instruction FormatFloating-Point Convert Instructions PALcode Instruction FormatFloating-Point/Integer Register Moves PALcode Instruction Format Page Instruction Type Section Instruction Set OverviewFloating-Point Subsets Subsetting RulesOpcode Qualifiers Software Emulation RulesOpcode Qualifiers Meaning Memory Integer Load/Store Instructions Mnemonic Operation Memory Integer Load/Store InstructionsLoad Address LDL Load Memory Data into Integer RegisterImplementation Notes Load Unaligned Memory Data into Integer Register Load Memory Data into Integer Register Locked 10Alpha Architecture Handbook Implementation Notes Store Integer Register Data into Memory Conditional Stqc BEQ Hardware/Software Implementation Note Store Integer Register Data into Memory 16Alpha Architecture Handbook Store Unaligned Integer Register Data into Memory Control Instructions Summary Mnemonic Operation Control InstructionsBSR BNEJMP JSRConditional Branch Unconditional Branch Jumps Encoding Meaning Count instruction CIX extension implementation note Integer Arithmetic InstructionsInteger Arithmetic Instructions Summary Mnemonic Operation Addl Longword AddS4ADDL Scaled Longword AddS8ADDL Addq Quadword AddS4ADDQ Scaled Quadword AddS8ADDQ Integer Signed Compare Integer Unsigned Compare Count Leading Zero Count Population Count Trailing Zero Mull Longword MultiplyMulq Quadword MultiplyUnsigned Quadword Multiply High Subl Longword SubtractS4SUBL Scaled Longword SubtractS8SUBL Subq Quadword SubtractS4SUBQ Scaled Quadword SubtractS8SUBQ Logical and Shift Instructions Summary Mnemonic Operation Logical and Shift InstructionsLogical Functions Conditional Move Integer Is exactly equivalent to Shift Logical Shift Arithmetic Instruction Meaning Described in Section Byte Manipulation InstructionsInslh InswhInsqh MskblBEQ Loop Compare ByteTo compare two character strings for greater/equal/less Extract Byte Ldqu Optimized examples Big-endian examples Byte Insert 56Alpha Architecture Handbook Byte Mask Insqh Inswh Sign Extend Zero Bytes Floating-Point Instructions Subsets and FaultsSingle-Precision Operations Alpha finite number DefinitionsDirty zero DenormalInfinity Non-finite numberTrue zero EncodingsSign Exponent Fraction Vax Meaning FiniteVAX Rounding Modes Rounding ModesIeee Rounding Modes Ieee Rounding Mode Instruction Notation VAX Rounding Mode Instruction NotationComputational Models VAX-Format Arithmetic with Precise ExceptionsIEEE-Compliant Arithmetic High-Performance VAX-Format ArithmeticIEEE-Compliant Arithmetic Without Inexact Exception High-Performance IEEE-Format Arithmetic Trapping ModesVAX Trapping Modes When /U or /V mode is specified Ieee Trapping Modes VAX Trapping Modes Summary Trap Mode Notation MeaningSUI Summary of Ieee Trapping Modes Trap Mode Notation MeaningSVI Arithmetic Trap CompletionTrap Shadow Length Rules Page Invalid Operation INV Arithmetic Trap Overflow OVF Arithmetic Trap Division by Zero DZE Arithmetic TrapUnderflow UNF Arithmetic Trap Ieee Floating-Point Trap Disable BitsInexact Result INE Arithmetic Trap Integer Overflow IOV Arithmetic TrapIeee Denormal Control Bits Floating-Point Control Register FpcrFloating-Point Control Register Fpcr Format Ieee Rounding Mode SelectedPage Accessing the Fpcr Saving and Restoring the Fpcr Default Values of the FpcrSoftware Notes Floating-Point Instruction Function Field Floating-Point Instruction Function Field FormatContents Meaning for Opcodes 1616 ITOFS/ITOFT FNCSQRTS/SQRTT Unpredictable Conversion of NaN and Infinity Values Ieee StandardGenerating NaN Values Copying NaN ValuesPropagating NaN Values Memory Format Floating-Point Instructions Load Ffloating Load Gfloating Load Sfloating Load Tfloating Store Ffloating Store Gfloating Store Sfloating Store Tfloating Branch Format Floating-Point Instructions FBxx Fa.rq,disp.al Branch format Page Floating-Point Operate Format Instructions Addg AddfAdds IeeeMulg MulfMuls MultCopy Sign Convert Integer to Integer Floating-Point Conditional Move Fcmovne F3,F2,F1 Move from/to Floating-Point Control Register VAX Floating Add Ieee Floating Add Cmpgeq VAX Floating CompareCmpgle CmpgltCmpteq Ieee Floating CompareCmptle CmptltConvert VAX Floating to Integer Convert Integer to VAX Floating Convert VAX Floating to VAX Floating Convert Ieee Floating to Integer Convert Integer to Ieee Floating Convert Ieee SFloating to Ieee TFloating Convert Ieee TFloating to Ieee SFloating VAX Floating Divide Ieee Floating Divide Floating-Point Register to Integer Register Move Integer Register to Floating-Point Register Move Itofs is exactly equivalent to the sequence VAX Floating Multiply Ieee Floating Multiply VAX Floating Square Root Ieee Floating Square Root VAX Floating Subtract Ieee Floating Subtract 17 Miscellaneous Instructions Summary Mnemonic Operation Miscellaneous InstructionsArchitecture Mask 134Alpha Architecture Handbook Call Privileged Architecture Library Evict Data Cache Block Implementation Note Exception Barrier Prefetch Data 140Alpha Architecture Handbook Implementation Version Memory Barrier Read Processor Cycle Counter Trap Barrier Write Hint Implementation Note Write Memory Barrier Processor Processor j 18 VAX Compatibility Instructions Summary Mnemonic Operation VAX Compatibility InstructionsVAX Compatibility Instructions Mnemonic Operation Multimedia Graphics and Video SupportByte and Word Minimum and Maximum Instruction mnemonics Pixel Error Pack Bytes Unpack Bytes Coherency of Memory Access Physical Address Space CharacteristicsIntroduction Software/Hardware Note Granularity of Memory AccessMemory-Like and Non-Memory-Like Behavior Width of Memory AccessCaches and Write Buffers Translation Buffers and Virtual CachesHardware/Software Coordination Note Page Data Sharing Atomic Update of a Single DatumAtomic Change of a Single Datum STQ Atomic Update of Data Structures8Alpha Architecture Handbook Ordering Considerations for Shared Data Structures Alpha Shared Memory Model Read/Write OrderingImplementation Note Definition of Processor Issue Constraints Architectural Definition of Processor Issue SequenceDefinition of Before and After 1st↓ 2nd → PiIn=4y,b PiRny,b PiWny,b PiMB PiIMB Processor Issue ConstraintsDefinition of Visibility Definition of Location Access ConstraintsDefinition of Storage Definition of Dependence Constraint Definition of Load-Locked and Store-Conditional Timeliness Litmus TestsLitmus Test 1 Impossible Sequence PiPjLitmus Test 3 Impossible Sequence Litmus Test 2 Impossible SequenceLitmus Test 5 Sequence Okay Litmus Test 4 Sequence OkayLitmus Test 6 Sequence Okay Litmus Test 8 Impossible Sequence Litmus Test 7 Impossible SequenceLitmus Test 10 Sequence Okay Litmus Test 9 Impossible SequenceLitmus Test 11 Impossible Sequence Implications for Software Implied BarriersSingle Processor Data Stream Single Processor Instruction StreamSee Footnote 1 on First Processor Second Processor Multiprocessor Context SwitchPage Multiprocessor Send/Receive Interrupt Implications for Memory Mapped I/O Multiple Processors Writing to a Single I/O Device Implications for Hardware Dictable Arithmetic TrapsPALcode Instructions and Functions PALcodeSpecial Functions Required for PALcode PALcode EnvironmentPALcode Effects on System Code PALcode ReplacementPALcode Instructions that Require Recognition Mnemonic Name Required PALcode InstructionsDraina Required PALcode Instructions Mnemonic Type OperationHalt IMBCallpal Draina Drain AbortsCallpal Halt HaltCallpal IMB Instruction Memory BarrierConsole Subsystem Overview Page Input/Output Overview Page Unprivileged OpenVMS Alpha PALcode OpenVMS AlphaChmk ChmeChms ChmuInsqhilr InsqhilInsqhiq InsqhiqrInsqtiq InsqtilrInsqtiqr InsquelReadunq RdpsREI RemqhilRemqtil RemqhiqrRemqtilr RemqtiqRemqueq RemquelRscc SwastenCflush Privileged OpenVMS Alpha PalcodeLdqp MfprSwpctx StqpWtint Page Mnemonic Operation and Description Unprivileged Digital Unix PALcodePrivileged Digital Unix PALcode 10-3 10-4Alpha Architecture Handbook Unprivileged Windows NT Alpha PALcode Instruction Summary Unprivileged Windows NT Alpha PALcodePrivileged Windows NT Alpha PALcode 11-3 11-4Alpha Architecture Handbook 11-5 Page Hardware-Software Compact Appendix aInstruction Alignment Instruction-Stream ConsiderationsBranch Prediction and Minimizing Branch-Taken Factor Figure A-1 Branch-Format BSR and BR Opcodes Improving I-Stream Density Factor Data-Stream ConsiderationsInstruction Scheduling Factor Data Alignment FactorShared Data in Multiple Processors Factor Avoiding Cache/TB Conflicts Factor Figure A-3 Bad Allocation in Cache Prefetching Factor Sequential Read/Write FactorCode Sequences Aligned Byte/Word Within Register Memory AccessesDivision Stylized Code Forms Byte Swap4.1 NOP Load Literal Clear a RegisterNegate Register-to-Register Move4.6 not BooleansPseudo-Operations Stylized Code Forms Exceptions and Trap BarriersSoftware Considerations A-15 Timing Considerations Atomic Sequences Alpha Choices for Ieee Options Appendix B2Alpha Architecture Handbook Alpha Support for OS Completion Handlers Figure B-1 Ieee Floating-Point Control FPC Quadword Ieee Floating-Point Control FPC QuadwordPage Mapping to Ieee Standard Figure B-2 Ieee Trap Handling Behavior Table B-2 Ieee Floating-Point Trap Handling User Hardware1 Completion Signal Alpha Instructions Code HandlerMULx Output Exceptions Cmptlt Cmptle Input Exceptions CVTff Output ExceptionsSQRTx Output Exceptions Overflow Division by ZeroUnderflow InexactCommon Architecture Instruction Summary Appendix CADDL/V Table C-2 Common Architecture InstructionsADDQ/V 15.0AF Convert Gfloating to quadword MULQ/V MULL/VSUBQ/V SUBL/VTable C-3 Ieee Floating-Point Instruction Function Codes Ieee Floating-Point InstructionsProgramming Note VAX Floating-Point InstructionsOpcode Summary Independent Floating-Point InstructionsTable C-6 Opcode Summary Table C-7 Key to Opcode Summary Symbol MeaningTable C-8 Common Architecture Opcodes in Numerical Order Common Architecture Opcodes in Numerical OrderInstruction Summary C-11 Addt Instruction Summary C-13 OpenVMS Alpha PALcode Instruction Summary Mfpresp MfprasnMfprfen MfpriplTable C-12 Digital Unix Privileged PALcode Instructions Digital Unix PALcode Instruction SummaryMnemonic Opcode Description Table C-14 Windows NT Alpha Privileged PALcode instructions Windows NT Alpha Instruction SummaryTable C-15 PALcode Opcodes in Numerical Order PALcode Opcodes in Numerical OrderWindows NT OpenVMS AlphaWtint 00.003F 00.0063 Opcodes Reserved to PALcode Required PALcode OpcodesTable C-16 Required PALcode Opcodes Mnemonic Type Table C-17 Opcodes Reserved for PALcode MnemonicUnused Function Code Behavior Opcodes Reserved to CompaqTable C-18 Opcodes Reserved for Compaq Mnemonic OPC01 OPC02 OPC03 OPC04 OPC05 OPC06 OPC07Table C-19 Ascii Character Set Hex Code Ascii Character SetProcessor Type Assignments Appendix DTable D-1 Processor Type Assignments Major Type Minor Type EV3PALcode Variation Assignments Table D-3 Amask Bit Assignments Bit Meaning Architecture Mask and Implementation ValuesTable D-4 Implver Value Assignments Meaning Digital UnixPage Waivers Appendix EDECchip 21264 LDxL/STxC with WH64 Violation DECchip 21064/21066/21068 Performance Monitoring Implementation-Specific FunctionalityFor the OpenVMS Alpha Operating System Functions and Arguments for the DECchip 21064/21066/21068 Disable performance monitoringSelect performance monitoring options Select desired events muxctl= PCMUX0 = PCMUX1Value Description PC1 PC0Performance Monitor Interrupt Mechanism DECchip 21164/21164PC Performance MonitoringWindows NT Alpha Functions and Argument Input Contents Register Bits MeaningCTR1 CTR0PCSEL0 Modeselect OpenVMS Alpha and Digital Unix Functions and ArgumentsPCSEL1 PCSEL2Select desired events Muxselect Disable performance monitoring do not reset countersRead the counters Select interrupt frequenciesOperate on counter MBZ MBZ PCSEL0MBZ PCSEL1 Bits Meaning Counters Operate Under These Modes When Bits SetS U P 6310 Table E-13 21164/21164PC Counter 1 PCSEL1 Event Selection Table E-14 21164/21164PC Counter 2 PCSEL2 Event Selection Value Meaning Table E-15 21164 CBOX1 Event SelectionTable E-16 21164 CBOX2 Event Selection Table E-18 21164PC PM1MUX Event Selection Table E-17 21164PC PM0MUX Event Selection3 21264 Performance Monitoring PCTR0 SEXTPCTR0CTL47IERCMPCEN0 PCTR1Bit value Meaning SL1Select logging options Enable and write selected counters R17/a1 Bits Meaning Table E-26 21264 Enable and Write Counters for OpenVMS Alpha Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13