Compaq ECQD2KCTE manual

The following requirements must be met by all cache/write-buffer implementations. All pro- cessors must provide a coherent view of memory.

•Write buffers may be used to delay and aggregate writes. From the viewpoint of another processor, buffered writes appear not to have happened yet. (Write buffers must not delay writes indefinitely. See Section 5.6.1.9.)

•Write-back caches must be able to detect a later write from another processor and inval- idate or update the cache contents.

•A processor must guarantee that a data store to a location followed by a data load from the same location reads the updated value.

•Cache prefetching is allowed, but virtual caches must not prefetch from invalid pages. See Sections 5.6.1.3, 5.6.4.3, and 5.6.4.4.

•A processor must guarantee that all of its previous writes are visible to all other proces- sors before a HALT instruction completes. A processor must guarantee that its caches are coherent with the rest of the system before continuing from a HALT.

•If battery backup is supplied, a processor must guarantee that the memory system remains coherent across a powerfail/recovery sequence. Data that was written by the processor before the powerfail may not be lost, and any caches must be in a valid state before (and if) normal instruction processing is continued after power is restored.

•Virtual instruction caches are not required to notice modifications of the virtual I-stream (they need not be coherent with the rest of memory). Software that creates or modifies the instruction stream must execute a CALL_PAL IMB before trying to exe- cute the new instructions.

In this context, to "modify the virtual I-stream" means either:

–any Store to the same physical address that is subsequently fetched as an instruction by some corresponding (virtual address, ASN) pair, or

–any change to the virtual-to-physical address mapping so that di fferent values are fetched.

For example, if two different virtual addresses, VA1 and VA2, map to the same page frame, a store to VA1 modifies the virtual I-stream fetched by VA2.

However, the following sequence does not modify the virtual I-stream (this might happen in soft page faults).

1.Change the mapping of an I-stream page from valid to invalid.

2.Copy the corresponding page frame to a new page frame.

3.Change the original mapping to be valid and point to the new page frame.

•Physical instruction caches are not required to notice modifications of the physical I-stream (they need not be coherent with the rest of memory), except for certain paging activity. (See Section 5.6.4.4.) Software that creates or modifies the instruction stream must execute a CALL_PAL IMB before trying to execute the new instructions.

In this context, to "modify the physical I-stream" means any Store to the same physical address that is subsequently fetched as an instruction.

System Architecture and Programming Implications 5–5