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Shift arithmetic instructions,
Sign extend instructions,
SLL instruction,
Software considerations,
See also Performance optimizations SQRTF instruction,
SQRTG instruction,
SQRTS instruction,
SQRTT instruction,
Square root instructions
IEEE,
VAX,
SRA instruction,
SRL instruction,
STB instruction,
STF instruction,
STG instruction,
STL instruction,
STL_C instruction,
when guaranteed ordering with LDL_L,
with processor lock register/flag,
Store instructions
emulation of,
FETCH instruction,
Store byte,
store longword conditional,
store quadword conditional,
STQ_U,
See also
STORE_CONDITIONAL operator,
STQ instruction,
STQ_C instruction,
when guaranteed ordering with LDQ_L,
with processor lock register/flag,
STS instruction,
STT instruction,
STW instruction,
SUBF instruction,
SUBG instruction,
SUBL instruction,
SUBQ instruction,
SUBS instruction,
SUBT instruction,
Subtract instructions
subtract longword,
SUM bit. See Summary bit Summary bit, in FPCR,
SWPPAL (PALcode) instruction required recognition of,
swppal (PALcode) instruction required recognition of,
T
T_floating data type
alignment of,
NaN with S_floating convert,
Timing considerations, atomic sequences,
Trap disable bits,
denormal operand exception,
DZED with DZE arithmetic trap,
inexact result,
Trap enable bits,
Trap handler, with
Trap handling, IEEE
Trap modes
Trap shadow
defined for