Shift arithmetic instructions, 4–46

Sign extend instructions, 4–60

Single-precision floating-point,4–62

SLL instruction, 4–45

Software considerations, A–1

See also Performance optimizations SQRTF instruction, 4–128

SQRTG instruction, 4–128

SQRTS instruction, 4–129

SQRTT instruction, 4–129

Square root instructions

IEEE, 4–129

VAX, 4–128

SRA instruction, 4–46

SRL instruction, 4–45

STB instruction, 4–15

STF instruction, 4–95

STG instruction, 4–96

STL instruction, 4–15

STL_C instruction, 4–12

when guaranteed ordering with LDL_L, 4–14with LDx_L instruction, 4–12

with processor lock register/flag, 4–12Storage, defined, 5–14

Store instructions

emulation of, 4–3

FETCH instruction, 4–139multiprocessor environment, 5–6serialization, 4–142

Store byte, 4–15store longword, 4–15

store longword conditional, 4–12store quadword, 4–15

store quadword conditional, 4–12Store word, 4–15

STQ_U, 4–17

See also Floating-point store instructions Store memory integer instructions, 4–4

STORE_CONDITIONAL operator, 3–9Store-conditional, defined, 5–16

STQ instruction, 4–15

STQ_C instruction, 4–12

when guaranteed ordering with LDQ_L, 4–14with LDx_L instruction, 4–12

with processor lock register/flag, 4–12STQ_U instruction, 4–17

STS instruction, 4–97with FPCR, 4–84

STT instruction, 4–98

STW instruction, 4–15

SUBF instruction, 4–130

SUBG instruction, 4–130

SUBL instruction, 4–37

SUBQ instruction, 4–39

SUBS instruction, 4–131

SUBT instruction, 4–131

Subtract instructions

subtract longword, 4–37subtract quadword, 4–39subtract scaled longword, 4–38subtract scaled quadword, 4–40 See also Floating-point operate

SUM bit. See Summary bit Summary bit, in FPCR, 4–80

SWPPAL (PALcode) instruction required recognition of, 6–4

swppal (PALcode) instruction required recognition of, 6–4

T

T_floating data type

alignment of, 2–9exceptions, 2–9format, 2–9MAX/MIN, 4–65

NaN with S_floating convert, 4–88TEST(x,cond) operator, 3–10Timeliness of location access, 5–17

Timing considerations, atomic sequences, A–16

Trap disable bits, 4–78

denormal operand exception, 4–81division by zero, 4–81

DZED with DZE arithmetic trap, 4–77DZED with INV arithmetic trap, 4–76IEEE compliance and, B–4

inexact result, 4–80invalid operation, 4–81overflow disable, 4–81underflow, 4–80underflow to zero, 4–80when unimplemented, 4–78

Trap enable bits, B–5

Trap handler, with non-finite arithmetic operands, 4–74

Trap handling, IEEE floating-point,B–6

Trap modes floating-point,4–69

Trap shadow

defined for floating-point,4–64programming implications for, 5–30

Index–11

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Compaq ECQD2KCTE manual Index-11