E.2.2 DECchip 21164/21164PC Performance Monitoring
Unless otherwise stated, the term "21164" in this section means implementations of the 21164 at all frequencies.
PALcode instructions control the DECchip 21164/21164PC
The instruction arguments and results are described in the following sections. The scratch reg- ister usage is operating system specific.
Three
Processes can be selectively monitored with the PME bit.
E.2.2.1 Performance Monitor Interrupt Mechanism
The performance monitoring interrupt mechanism varies according to the particular operating system.
For the OpenVMS Alpha Operating System
When a counter overflows and interrupt enabling conditions are correct, the counter causes an interrupt to PALcode. The PALcode builds an appropriate stack frame. The PALcode then dis- patches in the form of an exception (not in the form of an interrupt) to the operating system by v e c t o r i n g t o t h e S C B p e r f o r m a n c e m o n i t o r e n t r y p o i n t t h r o u g h S C B B + 6 5 0 (HWSCB$Q_PERF_MONITOR), at IPL 29, in kernel mode.
An interrupt is generated for each counter overflow. For each interrupt, the status of each counter overflow is indicated by register R4:
R4 = 0 if performance counter 0 caused the interrupt
R4 = 1 if performance counter 1 caused the interrupt
R4 = 2 if performance counter 2 caused the interrupt
When the interrupt is taken, the PC is saved on the stack frame as the old PC.
For the DIGITAL UNIX Operating System
When a counter overflows and interrupt enabling conditions are correct, the counter causes an interrupt to PALcode. The PALcode builds an appropriate stack frame and dispatches to the operating system by vectoring to the interrupt entry point entINT, at IPL 6, in kernel mode.
An interrupt is generated for each counter overflow. For each interrupt, registers a0..a2 are as follows:
a0 = osfint$c_perf (4)
a1 = scb$v_perfmon (650)
a2 = 0 if performance counter 0 caused the interrupt a2 = 1 if performance counter 1 caused the interrupt
Waivers and
