and accesses byte z; then the value of byte z read by v is exactly the value written by u. In this situation, u is a source of v.
The only way to communicate information between different processors is for one to write a shared location and the other to read the shared location and receive the newly written value. (In this context, the sending of an interrupt from processor Pi to Pj is modeled as Pi writing to a location INTij, and Pj reading from INTij.)
5.6.1.7 Definition of Dependence Constraint
The depends relation (DP) is defined as follows. Given u and v issued by processor Pi, where u is a read or an instruction fetch and v is a write, u precedes v in DP order (written u DP v, that is, v depends on u) in either of the following situations:
•u determines the execution of v, the location accessed by v, or the value written by v.
•u determines the execution or address or value of another memory access z that pre- cedes v or might precede v (that is, would precede v in some execution path depending on the value read by u) by processor issue constraint (see Section 5.6.1.3).
Note that the DP relation does not directly impose a BEFORE (⇐) ordering between accesses u and v.
The dependence constraint requires that the union of the DP relation and the "is a source of" relation (see Section 5.6.1.6) be acyclic. That is, there must not exist reads and/or
1.n ≥ 1,
2.For each i, 1 ≤ i ≤ n, Ri DP Wi,
3.For each i, 1 ≤ i < n, Wi is a source of Ri + 1, and
4.Wn is a source of R1.
That constraint eliminates the possibility of "causal loops." A simple example of a "causal loop" is when the execution of a write on Pi depends on the execution of a write on Pj and vice versa, creating a circular dependence chain. The following simple example of a "causal loop" is written in the style of the litmus tests in Section 5.6.2, where initially x and y are 1:
Processor Pi executes:
LDQ R1,x
STQ R1,y
Processor Pj executes:
LDQ R1,y
STQ R1,x
System Architecture and Programming Implications
