Compaq ECQD2KCTE manual Index-3

Changed datum, 5–6Clear a register, A–12CMOVEQ instruction, 4–43CMOVGE instruction, 4–43CMOVGT instruction, 4–43CMOVLBC instruction, 4–43CMOVLE instruction, 4–43CMOVLT instruction, 4–43CMOVNE instruction, 4–43CMPBGE instruction, 4–49CMPEQ instruction, 4–29CMPGLE instruction, 4–112CMPGLT instruction, 4–112CMPLE instruction, 4–29CMPLT instruction, 4–29CMPTEQ instruction, 4–113CMPTLE instruction, 4–113CMPTLT instruction, 4–113CMPTUN instruction, 4–113CMPULE instruction, 4–30CMPULT instruction, 4–30

Code forms, stylized, A–11

Boolean, A–13load literal, A–12negate, A–13NOP, A–11NOT, A–13register, clear, A–12

register-to-register move, A–13Code scheduling

IMPLVER instruction with, 4–141Code sequences, A–9

CODEC, 4–151

Coherency

cache, 5–2memory, 5–1

Compare instructions

compare integer signed, 4–29compare integer unsigned, 4–30 See also Floating-point operate

Conditional move instructions, 4–43 See also Floating-point operate

Console overview, 7–1

Control instructions, 4–18

Conventions

code examples, 1–9extents, 1–8figures, 1–9instruction format, 3–10

notation, 3–10numbering, 1–7ranges, 1–8

Count instructions

Count leading zero, 4–31Count population, 4–32Count trailing zero, 4–33

CPYS instruction, 4–105CPYSE instruction, 4–105CPYSN instruction, 4–105

CSERVE (PALcode) instruction required recognition of, 6–4

cserve (PALcode) instruction required recognition of, 6–4

CTLZ instruction, 4–31CTPOP instruction, 4–32CTTZ instruction, 4–33CVTDG instruction, 4–116CVTGD instruction, 4–116CVTGF instruction, 4–116CVTGQ instruction, 4–114CVTLQ instruction, 4–106CVTQF instruction, 4–115CVTQG instruction, 4–115

CVTQL instruction, 4–106

FP_C quadword with, B–5

CVTQS instruction, 4–118

CVTQT instruction, 4–118

CVTST instruction, 4–120

CVTTQ instruction, 4–117

FP_C quadword with, B–5

CVTTS instruction, 4–119

D

/D opcode qualifier

FPCR (floating-point control register), 4–79IEEE floating-point,4–67

D_floating data type, 2–5

alignment of, 2–6mapping, 2–6restricted, 2–6

Data alignment, A–4

Data caches

ECB instruction with, 4–136WH64 instruction with, 4–145

Data format, overview, 1–3

Data sharing (multiprocessor), A–5synchonization requirement, 5–6

Index–3