In most systems, DMA I/O devices or other agents can read or write shared memory locations. The order of accesses by those agents is not completely specified in this document. It is possi- ble in some systems for read accesses by I/O devices or other agents to give results indicating some reordering of accesses. However, there are guarantees that apply in all systems. See Sec- tion 5.6.4.7.
A shared memory is the primary storage place for one or more locations.
A location is a byte, specified by its physical address. Multiple virtual addresses may map to the same physical address. Ordering considerations are based only on the physical address. This definition of location specifically includes locations and registers in memory mapped I/O devices and bridges to remote I/O (for example, Mailbox Pointer Registers, or MBPRs).
Implementation Note:
An implementation may allow a location to have multiple physical addresses, but the rules for accesses via mixtures of the addresses are
Each processor may generate accesses to shared memory locations. There are six types of accesses:
1.Instruction fetch by processor i to location x, returning value a, denoted Pi:I<4>(x,a).
2.Data read (including
3.Data write (including successful
4.Memory barrier issued by processor i, denoted Pi:MB.
5.Write memory barrier issued by processor i, denoted Pi:WMB.
6.
The first access type is also called an
The last three types collectively are called barriers or memory barriers.
The size of a read/write access is 8 for a quadword access, 4 for a longword access (including all instruction fetches), 2 for a word access, or 1 for a byte access. All read/write accesses in this chapter are naturally aligned. That is, they have the form Pi:Op<m>(x,a), where the address x is divisible by size m.
The word "access" is also used as a verb; a read/write access Pi:Op<m>(x,a) accesses byte z if x ≤ z < x+m. Two read/write accesses Op1<m>(x,a) and Op2<n>(y,b) are defined to overlap if
System Architecture and Programming Implications
